Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCYBLE-416045-02 EZ-BLE Creator Module EZ-BLE Creator Module Low-Power 1.71 V to 3.6 V Operation General Description Active, Low-power Active, Sleep, Low-power Sleep, Deep The Cypress CYBLE-416045-02 is a fully certified and qualified Sleep, and Hibernate modes for fine-grained power module supporting Bluetooth Low Energy (BLE) wireless management communication. The CYBLE-416045-02 is a turnkey solution Deep Sleep mode current with 64K SRAM retention is 7 A and includes onboard crystal oscillators, trace antenna, passive with 3.3-V external supply and internal buck components, and the Cypress PSoC 63 BLE silicon device. Refer to the PSoC 63 BLE datasheet for additional details on the On-chip Single-In Multiple Out (SIMO) DC-DC Buck converter, capabilities of the PSoC 63 BLE device used on this module. less than 1 A quiescent current The EZ-BLE Creator module is a scalable and reconfigurable Backup domain with 64 bytes of memory and Real-Time-Clock platform architecture. It combines programmable and (RTC) programmable analog reconfigurable analog and digital blocks with flexible automatic routing. The CYBLE-416045-02 also includes digital Serial Communication programmable logic, high-performance analog-to-digital conversion (ADC), low-power comparators, and standard Five independent runtime reconfigurable serial communication 2 communication and timing peripherals. blocks (SCBs), each is software configurable as I C, SPI, or UART The CYBLE-416045-02 includes a royalty-free BLE stack compatible with Bluetooth 5.0 and provides up to 36 GPIOs in a Timing and Pulse-Width Modulation (TCPWM) 14 18.5 2.00 mm package. Thirty-two TCPWM blocks The CYBLE-416045-02 is a complete solution and an ideal fit for applications seeking a high-performance BLE wireless solution. Center-aligned, Edge, and Pseudo-random modes Module Description Comparator-based triggering of Kill signals Module size: 14.0 mm 18.5 mm 2.00 mm (with shield) Up to 36 Programmable GPIOs 1 MB Application Flash with 32-KB EEPROM area and 32-KB Any GPIO pin can be CapSense , analog/digital Secure Flash Audio Subsystem 288-KB SRAM with Selectable Retention Granularity 2 I S interface up to 192 kilosamples (ksps) word clock Up to 36 GPIOs with programmable drive modes, strengths, Two pulse-density modulation (PDM) channels for stereo digital and slew rates microphones Bluetooth 5.0 qualified single-mode module Programmable Analog QDID: D040144 12-bit 1 Msps SAR ADC with differential and single-ended Declaration ID:112778 modes and Sequencer with signal averaging Certified to FCC, CE, MIC, and ISED regulations One 12-bit voltage mode DAC with less than 5 s settling time Two opamps with low-power operation modes Industrial temperature range: 40 C to +85 C Two low-power comparators that operate in Deep Sleep and 150-MHz Arm Cortex -M4F CPU with single-cycle multiply Hibernate modes (Floating Point Unit (FPU) and Memory Protection Unit (MPU)) Built-in temperature sensor connected to ADC 100-MHz Cortex-M0+ CPU with single-cycle multiply and MPU Programmable Digital OTP eFuse memory for validation and security 12 programmable logic blocks, each with eight macrocells and an 8-bit data path (called universal digital blocks or UDBs) Power Consumption Usable as drag-and-drop Boolean primitives (gates, registers), TX output power: 20 dbm to +4 dbm or as Verilog programmable blocks Cypress-provided peripheral component library using UDBs to Received signal strength indication (RSSI) with 4-dB resolution implement functions such as communication peripherals (for 2 TX current consumption of 5.7 mA (radio only, 0 dbm) example, LIN, UART, SPI, I C, S/PDIF and other protocols), waveform generators, pseudo-random sequence (PRS) RX current consumption of 6.7 mA (radio only) generation, and other functions. Smart I/O (Programmable I/O) blocks enable Boolean operations on signals coming from, and going to, GPIO pins Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-24085 Rev. *A Revised February 21, 2019