Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comPSoC 4: PSoC 4100PS Datasheet Programmable System-on-Chip (PSoC) General Description Cypress PSoC 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an Arm Cortex-M0+ CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. PSoC 4100PS is a member of the PSoC 4 platform architecture. It is a combination of a microcontroller with standard communication and timing peripherals, a capacitive touch-sensing system (CapSense) with best-in-class performance, programmable general-purpose continuous-time and switched-capacitor analog blocks, and programmable connectivity. Features Programmable Analog Blocks Low-Power Operation Two dedicated analog-to-digital converters (ADC) including a 1.71-V to 5.5-V operation 12-bit SAR ADC and a 10-bit single-slope ADC Deep-Sleep mode with operational analog and 2.5-A digital Four opamps, two low-power comparators, and a flexible system current 38-channel analog mux to create custom Analog Front Ends Watch Crystal Oscillator (WCO) (AFE) Programmable GPIO Pins Two 13-bit Voltage DACs Up to 38 GPIOs that can be used for analog, digital, CapSense, Two 7-bit Current DACs (IDACs) for general-purpose or capac- or LCD functions with programmable drive modes, strength and itive sensing applications on any pin slew rates CapSense Capacitive Sensing Includes eight Smart I/Os to implement pin-level Boolean Cypress s fourth-generation CapSense Sigma-Delta (CSD) operations on input and output signals providing best-in-class signal-to-noise ratio (SNR) and water 48-pin QFN, 48-pin TQFP, 28-pin SSOP, and 45-ball WLCSP tolerance packages Cypress-supplied software component makes capacitive PSoC Creator Design Environment sensing design easy Integrated Design Environment (IDE) provides Automatic hardware tuning (SmartSense) schematic-capture design entry and build (with automatic Segment LCD Drive routing of analog and digital signals) and concurrent firmware development with an Arm-SWD debugger LCD drive supported on all pins (common or segment) GUI-based configurable PSoC Components with fully Operates in Deep-Sleep mode with four bits per pin memory engineered embedded initialization, calibration and correction algorithms Programmable Digital Peripherals Application Programming Interfaces (API) for all fixed-function Three independent serial communication blocks (SCBs) that and programmable peripherals are run-time configurable as I2C, SPI or UART Industry-Standard Tool Compatibility Eight 16-bit timer/counter/pulse-width modulator (TCPWM) blocks with center-aligned, edge, and pseudo-random modes After schematic-capture, firmware development can be done with Arm-based industry-standard development tools 32-bit Signal Processing Engine Arm Cortex-M0+ CPU up to 48 MHz Up to 32 KB of flash with read accelerator Up to 4 KB of SRAM Eight-channel descriptor-based DMA controller Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-22097 Rev. *E Revised December 17, 2020