PSoC 3: CY8C38 Family Data Sheet Programmable System-on-Chip (PSoC ) General Description With its unique array of configurable blocks, PSoC 3 is a true system level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C38 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals. The CY8C38 family can handle dozens of data acquisition channels and analog inputs on every general-purpose input/output (GPIO) pin. The CY8C38 family is also a high-performance configurable digital system with some 2 part numbers including interfaces such as USB, multimaster inter-integrated circuit (I C), and controller area network (CAN). In addition to communication interfaces, the CY8C38 family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance single cycle 8051 microprocessor core. You can easily create system-level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator, a hierarchical schematic design entry tool. The CY8C38 family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates. Library of standard peripherals Features 8-, 16-, 24-, and 32-bit timers, counters, and PWMs Single cycle 8051 CPU Serial peripheral interface (SPI), universal asynchronous DC to 67 MHz operation 2 transmitter receiver (UART), and I C Multiply and divide instructions Many others available in catalog Flash program memory, up to 64 KB, 100,000 write cycles, Library of advanced peripherals 20 years retention, and multiple security features Cyclic redundancy check (CRC) Up to 8-KB flash error correcting code (ECC) or configuration Pseudo random sequence (PRS) generator storage Local interconnect network (LIN) bus 2.0 Up to 8 KB SRAM Quadrature decoder Up to 2 KB electrically erasable programmable read-only Analog peripherals (1.71 V V 5.5 V) memory (EEPROM), 1 M cycles, and 20 years retention DDA 1.024 V 0.1% internal voltage reference across 40 C to 24-channel direct memory access (DMA) with multilayer 1 +85 C (14 ppm/C) AHB bus access Configurable delta-sigma ADC with 8- to 20-bit resolution Programmable chained descriptors and priorities Sample rates up to 192 ksps High bandwidth 32-bit transfer support Programmable gain stage: 0.25 to 16 Low voltage, ultra low-power 12-bit mode, 192 ksps, 66-dB signal to noise and distortion Wide operating voltage range: 0.5 V to 5.5 V ratio (SINAD), 1-bit INL/DNL High efficiency boost regulator from 0.5-V input through 1.8-V 16-bit mode, 48 ksps, 84-dB SINAD, 2-bit INL, 1-bit DNL to 5.0-V output Up to four 8-bit, 8-Msps IDACs or 1-Msps VDACs 0.8 mA at 3 MHz, 1.2 mA at 6 MHz, and 6.6 mA at 48 MHz Four comparators with 95-ns response time Low-power modes including: Up to four uncommitted opamps with 25-mA drive capability 1-A sleep mode with real time clock and low-voltage Up to four configurable multifunction analog blocks. Example detect (LVD) interrupt configurations are programmable gain amplifier (PGA), 200-nA hibernate mode with RAM retention transimpedance amplifier (TIA), mixer, and sample and hold Versatile I/O system CapSense support 28 to 72 I/O (62 GPIOs, eight special input/outputs (SIO), 2 Programming, debug, and trace two USBIOs ) JTAG (4-wire), serial wire debug (SWD) (2-wire), and single Any GPIO to any digital or analog peripheral routability 2 wire viewer (SWV) interfaces LCD direct drive from any GPIO, up to 46 16 segments 3 Eight address and one data breakpoint CapSense support from any GPIO 4-KB instruction trace buffer 1.2-V to 5.5-V I/O interface voltages, up to four domains 2 Bootloader programming supportable through I C, SPI, Maskable, independent IRQ on any pin or port UART, USB, and other interfaces Schmitt-trigger transistor-transistor logic (TTL) inputs Precision, programmable clocking All GPIO configurable as open drain high/low, 3- to 62-MHz internal oscillator over full temperature and pull-up/pull-down, High Z, or strong output voltage range Configurable GPIO pin state at power-on reset (POR) 4- to 25-MHz crystal oscillator for crystal PPM accuracy 25 mA sink on SIO Internal PLL clock generation up to 67 MHz Digital peripherals 32.768-kHz watch crystal oscillator 20 to 24 programmable logic device (PLD) based universal Low-power internal oscillator at 1, 33, and 100 kHz digital blocks (UDB) 2 Temperature and packaging Full CAN 2.0b 16 Rx, 8 Tx buffers 2 40C to +85 C degrees industrial temperature Full-speed (FS) USB 2.0 12 Mbps using internal oscillator 48-pin SSOP, 48-pin QFN, 68-pin QFN, and 100-pin TQFP Up to four 16-bit configurable timer, counter, and PWM blocks package options 67 MHz, 24-bit fixed point digital filter block (DFB) to implement FIR and IIR filters Notes 1. AHB AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus 2. This feature on select devices only. See Ordering Information on page 116 for details. 3. GPIOs with opamp outputs are not recommended for use with CapSense. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-11729 Rev. *R Revised March 30, 2011 + Feedback PSoC 3: CY8C38 Family Data Sheet Contents 1. Architectural Overview .................................................... 3 8.6 LCD Direct Drive ..................................................... 58 8.7 CapSense ................................................................ 59 2. Pinouts .............................................................................. 5 8.8 Temp Sensor ........................................................... 59 3. Pin Descriptions ............................................................. 10 8.9 DAC ......................................................................... 59 4. CPU .................................................................................. 11 8.10 Up/Down Mixer ...................................................... 60 4.1 8051 CPU ................................................................ 11 8.11 Sample and Hold ................................................... 60 4.2 Addressing Modes ................................................... 11 9. Programming, Debug Interfaces, Resources ............... 61 4.3 Instruction Set ......................................................... 11 9.1 JTAG Interface ........................................................ 61 4.4 DMA and PHUB ...................................................... 15 9.2 Serial Wire Debug Interface .................................... 61 4.5 Interrupt Controller .................................................. 17 9.3 Debug Features ....................................................... 62 5. Memory ............................................................................ 21 9.4 Trace Features ........................................................ 62 5.1 Static RAM .............................................................. 21 9.5 Single Wire Viewer Interface ................................... 62 5.2 Flash Program Memory ........................................... 21 9.6 Programming Features ............................................ 62 5.3 Flash Security .......................................................... 21 9.7 Device Security ....................................................... 62 5.4 EEPROM ................................................................. 21 10. Development Support .................................................. 63 5.5 Nonvolatile Latches (NVLs) ..................................... 22 10.1 Documentation ...................................................... 63 5.6 External Memory Interface ...................................... 23 10.2 Online .................................................................... 63 5.7 Memory Map ........................................................... 24 10.3 Tools ...................................................................... 63 6. System Integration ......................................................... 26 11. Electrical Specifications .............................................. 64 6.1 Clocking System ...................................................... 26 11.1 Absolute Maximum Ratings ................................... 64 6.2 Power System ......................................................... 29 11.2 Device Level Specifications ................................... 65 6.3 Reset ....................................................................... 32 11.3 Power Regulators .................................................. 69 6.4 I/O System and Routing .......................................... 33 11.1 Inputs and Outputs ................................................ 73 7. Digital Subsystem .......................................................... 39 11.2 Analog Peripherals ................................................ 80 7.1 Example Peripherals ............................................... 40 11.3 Digital Peripherals ................................................. 99 7.2 Universal Digital Block ............................................. 42 11.4 Memory ............................................................... 103 7.3 UDB Array Description ............................................ 46 11.5 PSoC System Resources .................................... 108 7.4 DSI Routing Interface Description ...........................46 11.6 Clocking ............................................................... 111 7.5 CAN ......................................................................... 48 12. Ordering Information .................................................. 115 7.6 USB ......................................................................... 49 12.1 Part Numbering Conventions ..............................117 7.7 Timers, Counters, and PWMs ................................. 50 2 13. Packaging .................................................................... 118 7.8 I C ...........................................................................50 7.9 Digital Filter Block .................................................... 51 14. Acronyms .................................................................... 122 8. Analog Subsystem ......................................................... 51 15. Reference Documents ................................................ 123 8.1 Analog Routing ........................................................ 52 16. Document Conventions ............................................. 123 8.2 Delta-sigma ADC ..................................................... 54 16.1 Units of Measure ................................................. 123 8.3 Comparators ............................................................ 55 17. Revision History ......................................................... 125 8.4 Opamps ................................................................... 56 18. Sales, Solutions, and Legal Information ...................129 8.5 Programmable SC/CT Blocks .................................57 Document Number: 001-11729 Rev. *R Page 2 of 129 + Feedback