Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY8C24094/CY8C24794 CY8C24894/CY8C24994 PSoC Programmable System-on-Chip PSoC Programmable System-on-Chip Up to 48 analog inputs on GPIOs Features Two 33 mA analog outputs on GPIOs XRES pin to support in-system serial programming (ISSP) and Configurable interrupt on all GPIOs external reset control in CY8C24894 Precision, programmable clocking Powerful Harvard-architecture processor Internal 4% 24- / 48-MHz main oscillator M8C processor speeds up to 24 MHz Internal oscillator for watchdog and sleep Two 8 8 multiply, 32-bit accumulate 0.25% accuracy for USB with no external components Low power at high speed Additional system resources Operating voltage: 3 V to 5.25 V 2 I C slave, master, and multi-master to 400 kHz Industrial temperature range: 40 C to +85 C Watchdog and sleep timers USB temperature range: 10 C to +85 C User-configurable low-voltage detection (LVD) Advanced peripherals (PSoC Blocks) Six rail-to-rail analog PSoC blocks provide: Logic Block Diagram Up to 14-bit analog-to-digital converters (ADCs) Up to 9-bit digital-to-analog converters (DACs) Analog Programmable gain amplifiers (PGAs) Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Port 7 Drivers Programmable filters and comparators Four digital PSoC blocks provide: 8- to 32-bit timers, counters, and pulse width modulators (PWMs) Cyclical redundancy check (CRC) and pseudo random Global Digital Interconnect sequence (PRS) modules Global Analog Interconnect Full-duplex universal asynchronous receiver transmitter PSoC CORE (UART) SRAM SROM Flash 16 KB Multiple serial peripheral interface (SPI) masters or slaves 1K Sleep and CPU Core (M8C) Watchdog Connectable to all general-purpose I/O (GPIO) pins Interrupt Controller Complex peripherals by combining blocks Clock Sources Capacitive sensing application (CSA) capability (Includes IMO and ILO) Full speed USB (12 Mbps) Four unidirectional endpoints DIGITAL SYSTEM ANALOG SYSTEM One bidirectional control endpoint Analog USB 2.0 compliant Ref. Dedicated 256 byte buffer Digital Analog Block Block No external crystal required Array Array Flexible on-chip memory 16 KB flash program storage 50,000 erase and write cycles 1 KB static random access memory (SRAM) data storage ISSP Partial flash updates Flexible protection modes Analog Internal Digital 2 Decimator 2 POR and LVD I C Voltage USB Input Electrically erasable programmable read-only memory Clocks MACs Type 2 System Resets Ref. Muxing (EEPROM) emulation in flash SYSTEM RESOURCES Programmable pin configurations 25-mA sink, 10-mA source on all GPIOs Pull-up, pull-down, high Z, strong, or open-drain drive modes on all GPIOs Errata: For information on silicon errata, see Errata on page 64. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-12018 Rev. AN Revised January 23, 2019 s System Bu