CY8C24123A CY8C24223A CY8C24423A PSoC Programmable System-on-Chip PSoC Programmable System-on-Chip New CY8C24x23A PSoC device Features Derived from the CY8C24x23 device Powerful Harvard-architecture processor Low power and low voltage (2.4 V) M8C processor speeds up to 24 MHz Additional system resources 8 8 multiply, 32-bit accumulate 2 I C slave, master, and multi-master to 400 kHz Low power at high speed Watchdog and sleep timers Operating voltage: 2.4 V to 5.25 V User-configurable low-voltage detection (LVD) Operating voltages down to 1.0 V using on-chip switch mode Integrated supervisory circuit pump (SMP) On-chip precision voltage reference Industrial temperature range: 40 C to +85 C Complete development tools Advanced peripherals (PSoC blocks) Free development software (PSoC Designer) Six rail-to-rail analog PSoC blocks provide: Full-featured, in-circuit emulator (ICE), and programmer Up to 14-bit analog-to-digital converters (ADCs) Full-speed emulation Up to 9-bit digital-to-analog converters (DACs) Complex breakpoint structure Programmable gain amplifiers (PGAs) 128 KB trace memory Programmable filters and comparators Four digital PSoC blocks provide: 8- to 32-bit timers and counters, 8- and 16-bit pulse-width Logic Block Diagram modulators (PWMs) Analog Port 2 Port 1 Port 0 Cyclical redundancy check (CRC) and pseudo random Drivers PSoC CORE sequence (PRS) modules Full-duplex universal asynchronous receiver transmitter (UART) System Bus Multiple serial peripheral interface (SPI) masters or slaves Global Digital Interconnect Can connect to all general-purpose I/O (GPIO) pins Global Analog Interconnect Complex peripherals by combining blocks SRAM SROM Flash 4KB 256 Bytes Precision, programmable clocking CPU Core (M8C) Sleep and Interrupt Internal 5% 24- / 48-MHz main oscillator Watchdog Controller High accuracy 24 MHz with optional 32 kHz crystal and phase-locked loop (PLL) Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO) Optional external oscillator up to 24 MHz Internal oscillator for watchdog and sleep DIGITAL SYSTEM ANALOG SYSTEM Flexible on-chip memory Analog 4 KB flash program storage 50,000 erase/write cycles Ref Digital Analog 256-bytes SRAM data storage Block Block Array Array In-system serial programming (ISSP) Analog Input Partial flash updates Muxing Flexible protection modes Electronically erasable programmable read only memory (EEPROM) emulation in flash Programmable pin configurations Internal Switch Digital Multiply POR and LVD 2 Decimator Voltage Mode I C 25-mA sink, 10-mA source on all GPIOs Clocks Accum. System Resets Ref. Pump Pull-up, pull-down, high Z, strong, or open-drain drive modes SYSTEM RESOURCES on all GPIOs Eight standard analog inputs on all GPIOs, and four additional analog inputs with restricted routing Two 30 mA analog outputs on all GPIOs Configurable interrupt on all GPIOs Errata: For information on silicon errata, see Errata on page 67. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-12028 Rev. *W Revised May 3, 2017 CY8C24123A CY8C24223A CY8C24423A More Information Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device for your design, and to help you to quickly and effectively integrate the device into your design. Following is an abbreviated list for PSoC 1: Overview: PSoC Portfolio, PSoC Roadmap Visit the PSoC 1 TRM page for the complete list of TRMs. Following documents provide detailed descriptions of the Ar- Product Selectors: PSoC 1, PSoC 3, PSoC 4, or PSoC 5LP chitecture, Programming specification and Register map de- In addition, PSoC Designer offers a device selection tool within tails of CY8C2XXXX PSoC 1 device family. PSoC 1, at the time of creating a new project. PSoC1 CY8C2XXXX TRM Datasheets: Describe and provide electrical specifications for PSoC1 ISSP Programming Specifications all the PSoC 1 family of devices. Visit the PSoC 1 datasheets web page for a complete list Development Kits: CY3210 - CY8C24x23 PSoC(R) Evaluation Pods (EvalPod) Application notes and code examples: are 28-pin PDIP adapters that seamlessly connect any PSoC Visit the PSoC 1 Code Examples web page for a comprehen- device to the 28-pin PDIP connector on any Cypress PSoC sive list of code examples development kit. CY3210-24x23 provides evaluation of the Cypress offers a large number of PSoC application notes CY8C24x23A PSoC device family on any PSoC developer covering a broad range of topics, from basic to advanced kit. PSoC developer kits are sold separately. level. Recommended application notes for getting started Visit the PSoC 1 Kits page and refer the Kit Selector Guide with PSoC 1 are: document to find out the suitable development kits and AN75320: Getting Started with PSoC 1 debuggers for all PSoC 1 families. AN2094: PSoC 1 - Getting Started with GPIO The CY3217-MiniProg1 and CY8CKIT-002 PSoC MiniProg3 AN2015: PSoC 1 - Getting Started with Flash & E2PROM device provide an interface for flash programming. AN2014: Basics of PSoC 1 Programming Knowledge Base Articles (KBA): Provide design and appli- AN32200: PSoC 1 - Clocks and Global Resources cation tips from experts on the devices/kits. For example, Flash AN2010: PSoC 1 Best Practices and Recommendations read/write access from firmware, explains how we can read and write to flash in PSoC 1 devices Technical Reference Manual (TRM): PSoC Designer PSoC Designer is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design of systems based on CapSense (see Figure 1). With PSoC Designer, you can: 1. Drag and drop user modules to build your hardware system 3. Configure user module design in the main design workspace 4. Explore the library of user modules 2. Codesign your application firmware with the PSoC hardware, 5. Review user module datasheets using the PSoC Designer IDE C compiler Figure 1. PSoC Designer Features 1 2 3 5 4 Document Number: 38-12028 Rev. *W Page 2 of 71