Product Information

CY7C53150-20AXIT

CY7C53150-20AXIT electronic component of Infineon

Datasheet
Network Controller & Processor ICs Neuron Chip External Memory Bus IND

Manufacturer: Infineon
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (AUD)

1: AUD 26.5011 ( AUD 29.15 Inc GST) ea
Line Total: AUD 26.5011 ( AUD 29.15 Inc GST)

0 - Global Stock
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
0 - Global Stock


Ships to you between Thu. 18 Jul to Mon. 22 Jul

MOQ : 1
Multiples : 1
1 : AUD 108.2946
10 : AUD 104.5792
25 : AUD 101.8369
50 : AUD 99.9262
100 : AUD 95.22
250 : AUD 95.22
500 : AUD 95.22
1000 : AUD 91.7346
1500 : AUD 91.7169

     
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Notes:- Show Stocked Products With Similar Attributes.

CY7C53150, CY7C53120 Neuron Chip Network Processor Features Three 8-bit pipelined processors for concurrent processing of On-chip LVD circuit to prevent nonvolatile memory corruption application code and network traffic during voltage drops 11-pin I/O port programmable in 34 modes for fast application 2,048 bytes of SRAM for buffering network data, system, and program development application data storage Two 16-bit timer/counters for measuring and generating I/O 512 bytes (CY7C53150), 2048 bytes (CY7C53120E2), 4096 device waveforms bytes (CY7C53120E4) of Flash memory with on-chip charge pump for flexible storage of configuration data and application 5-pin communication port that supports direct connect and code network transceiver interfaces Addresses up to 58 KB of external memory (CY7C53150) Programmable pull-ups on I/O4I/O7 and 20 mA sink current on I/O0I/O3 10 KB (CY7C53120E2), 12 KB (CY7C53120E4) of ROM containing LonTalk network protocol firmware Unique 48-bit ID number in every device to facilitate network installation and management Maximum input clock operation of 20 MHz (CY7C53150), 10 MHz (CY7C53120E2), 40 MHz (CY7C53120E4) over a Low operating current sleep mode operation for reduced 2 40C to 85C temperature range 1 current consumption 64-pin TQFP package (CY7C53150) 0.35 m flash process technology 32-pin SOIC or 44-pin TQFP package (CY7C53120) 5.0 V operation Logic Block Diagram CP4 Media Access Communications Control Processor Port CP0 I/O10 Network Internal I/O Block Processor Data Bus I/O0 (0:7) Application 2 Timer/ Processor Counters Internal Address Bus (0:15) 2 KB RAM CLK1 Oscillator, CLK2 Clock, and SERVICE Control Flash RESET External ROM Address/Data Bus (CY7C53120) (CY7C53150) Notes 1. Rare combinations of wake-up events occurring during the go to sleep sequence could produce unexpected sleep behavior. 2. Maximum Junction Temperature is 105 C. T = T + VI . 32-pin SOIC = 51 C/W. 44-pin TQFP = 43 C/W. 64-pin TQFP = 44 C/W. Junction Ambient JA JA JA JA Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-10001 Rev. *L Revised May 16, 2017 CY7C53150, CY7C53120 Contents Functional Description .....................................................3 External Memory Interface Timing CY7C53150 ....... 10 Pin Configurations ...........................................................4 Differential Transceiver Electrical Characteristics ...... 10 Pin Descriptions ...............................................................6 Ordering Information 23 ............................................... 14 Memory Usage ..................................................................7 Ordering Code Definitions ......................................... 14 Flash Memory Retention and Endurance .......................7 Package Diagrams .......................................................... 15 40 MHz 3120 Operation ....................................................7 Acronyms ........................................................................17 Low Voltage Inhibit Operation .........................................7 Document Conventions ................................................. 17 Communications Port ......................................................7 Units of Measure ....................................................... 17 Programmable Hysteresis Values ...............................8 Document History Page ................................................. 18 7 Programmable Glitch Filter Values ...........................8 Sales, Solutions, and Legal Information ...................... 19 8 Receiver (End-to-End) Absolute Asymmetry ...........8 Worldwide Sales and Design Support ....................... 19 Differential Receiver (End-to-End) Products ....................................................................19 9, 10 Absolute Symmetry .....................................................8 PSoC Solutions ...................................................... 19 Electrical Characteristics .................................................9 Cypress Developer Community ................................. 19 LVI Trip Point (V ...........................................................9 Technical Support ..................................................... 19 DD) Document Number: 38-10001 Rev. *L Page 2 of 19

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

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