CY7C4255V
CY7C4275V
CY7C4285V
8 K/32 K/64 K 18 Low Voltage
Deep Sync FIFOs
8 K/32 K/64 K 18 Low Voltage Deep Sync FIFOs
Features Functional Description
3.3 V operation for low power consumption and easy integration The CY7C4255/75/85V are high speed, low power, first-in
into low voltage systems first-out (FIFO) memories with clocked read and write interfaces.
All are 18 bits wide and are pin and functionally compatible to the
High speed, low power, first-in first-out (FIFO) memories
CY7C42X5V Synchronous FIFO family. The CY7C4255/75/85V
can be cascaded to increase FIFO depth. Programmable
8 K 18 (CY7C4255V)
features include Almost Full/Almost Empty flags. These FIFOs
32 K 18 (CY7C4275V)
provide solutions for a wide variety of data buffering needs,
including high speed data acquisition, multiprocessor interfaces,
64 K 18 (CY7C4285V)
and communications buffering.
0.35 micron CMOS for optimum speed and power
These FIFOs have 18-bit input and output ports that are
controlled by separate clock and enable signals. The input port
High speed 100 MHz operation (10 ns read/write cycle times)
is controlled by a free-running clock (WCLK) and a write enable
Low power
pin (WEN).
I = 30 mA
CC
When WEN is asserted, data is written into the FIFO on the rising
I = 4 mA
SB
edge of the WCLK signal. While WEN is held active, data is
continually written into the FIFO on each cycle. The output port
Fully asynchronous and simultaneous read and write operation
is controlled in a similar manner by a free-running read clock
Empty, Full, Half Full, and programmable Almost Empty and
(RCLK) and a read enable pin (REN). In addition, the
Almost Full status flags
CY7C4255/75/85V have an output enable pin (OE). The read
and write clocks may be tied together for single-clock operation
Retransmit function
or the two clocks may be run independently for asynchronous
Output Enable (OE) pin read or write applications. Clock frequencies up to 67 MHz are
achievable.
Independent read and write enable pins
Retransmit and Synchronous Almost Full/Almost Empty flag
Supports free running 50% duty cycle clock inputs
features are available on these devices.
Width Expansion Capability Depth expansion is possible using the cascade input (WXI, RXI),
cascade output (WXO, RXO), and First Load (FL) pins. The
Depth Expansion Capability
WXO and RXO pins are connected to the WXI and RXI pins of
the next device, and the WXO and RXO pins of the last device
64-pin 10 10 STQFP
must be connected to the WXI and RXI pins of the first device.
Pin compatible density upgrade to CY7C42X5V-ASC families
The FL pin of the first device is tied to VSS and the FL pin of all
the remaining devices must be tied to VCC.
Pin compatible 3.3 V solutions for CY7C4255/75/85V
For a complete list of related documentation, click here.
Selection Guide
Parameter 7C4255/75/85V-10 7C4255/75/85V-15
Maximum Frequency (MHz) 100 66.7
Maximum Access Time (ns) 8 10
Minimum Cycle Time (ns) 10 15
Minimum Data or Enable Setup (ns) 3.5 4
Minimum Data or Enable Hold (ns) 0 0
Maximum Flag Delay (ns) 8 10
Active Power Supply Current (I ) (mA) Commercial 30 30
CC1
Industrial 35
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 38-06012 Rev. *F Revised November 20, 2014CY7C4255V
CY7C4275V
CY7C4285V
Parameter CY7C4255V CY7C4275V CY7C4285V
Density 8 K 18 32 K 18 64 K 18
Package 64-pin 10 10 TQFP 64-pin 10 10 TQFP 64-pin 10 10 TQFP
Logic Block Diagram
D
0 17
INPUT
REGISTER
WCLK WEN
FLAG
PROGRAM
WRITE
REGISTER
CONTROL
High
FF
Density
EF
Dual-Port
FLAG
PAE
RAM Array LOGIC
PAF
8 K x 18
SMODE
32 K x 18
64 K x 18
WRITE READ
POINTER POINTER
RS
RESET
LOGIC
FL/RT
THREE-STATE
READ
WXI
OUTPUTREGISTER
EXPANSION
CONTROL
WXO/HF
LOGIC
RXI
OE
Q
RXO 0 17
RCLK
REN
Document Number: 38-06012 Rev. *F Page 2 of 25