Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY7C1354CV25 CY7C1356CV25 9-Mbit (256K 36/512K 18) Pipelined SRAM with NoBL Architecture 9-Mbit (256K 36/512K 18) Pipelined SRAM with NoBL Architecture Features Functional Description 1 Pin-compatible with and functionally equivalent to ZBT The CY7C1354CV25/CY7C1356CV25 are 2.5V, 256K 36/512K 18 synchronous pipelined burst SRAMs with Supports 250 MHz bus operations with zero wait states No Bus Latency (NoBL) logic, respectively. They are designed to support unlimited true back-to-back read/write Available speed grades are 250, 200, and 166 MHz operations with no wait states. The Internally self-timed output buffer control to eliminate the need CY7C1354CV25/CY7C1356CV25 are equipped with the to use asynchronous OE advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock Fully registered (inputs and outputs) for pipelined operation cycle. This feature dramatically improves the throughput of data Byte write capability in systems that require frequent write/read transitions. The CY7C1354CV25/CY7C1356CV25 are pin-compatible with and Single 2.5 V power supply (V ) DD functionally equivalent to ZBT devices. Fast clock-to-output times All synchronous inputs pass through input registers controlled by 2.8 ns (for 250-MHz device) the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock Clock enable (CEN) pin to suspend operation input is qualified by the clock enable (CEN) signal, which when deasserted suspends operation and extends the previous clock Synchronous self-timed writes cycle. Available in Pb-free 100-pin TQFP package, Pb-free and Write operations are controlled by the byte write selects non Pb-free 119-ball BGA package and 165-ball FBGA (BW BW for CY7C1354CV25 and BW BW for a d a b package CY7C1356CV25) and a write enable (WE) input. All writes are IEEE 1149.1 JTAG-compatible boundary scan conducted with on-chip synchronous self-timed write circuitry. Three synchronous chip enables (CE , CE , CE ) and an Burst capability linear or interleaved burst order 1 2 3 asynchronous output enable (OE) provide for easy bank ZZ sleep mode option and stop clock option selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. For a complete list of related documentation, click here. Selection Guide Description 250 MHz 200 MHz 166 MHz Unit Maximum access time 2.8 3.2 3.5 ns Maximum operating current 250 220 180 mA Maximum CMOS standby current 40 40 40 mA Note 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05537 Rev. *S Revised April 5, 2019