Product Information

CY7C1061GN30-10ZSXI

Hot CY7C1061GN30-10ZSXI electronic component of Infineon

Datasheet
2.2V~3.6V 16Mbit TSOPII-54 SRAM ROHS

Manufacturer: Infineon
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (AUD)

1: AUD 39.9191 ( AUD 43.91 Inc GST) ea
Line Total: AUD 39.9191 ( AUD 43.91 Inc GST)

96 - Global Stock
Ships to you between
Fri. 19 Jul to Wed. 24 Jul
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
96 - Global Stock


Ships to you between
Fri. 19 Jul to Wed. 24 Jul

MOQ : 1
Multiples : 1
1 : AUD 39.9191
10 : AUD 34.9345
30 : AUD 34.0273
100 : AUD 33.2355

479 - Global Stock


Ships to you between Thu. 18 Jul to Mon. 22 Jul

MOQ : 1
Multiples : 1
1 : AUD 86.2146
10 : AUD 81.5615
25 : AUD 76.6608
50 : AUD 76.5546
100 : AUD 70.6631
250 : AUD 70.6631
540 : AUD 70.6631
1080 : AUD 70.6631

     
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Notes:- Show Stocked Products With Similar Attributes.

CY7C1061GN/CY7C10612GN 16-Mbit (1M words 16 bit) Static RAM 16-Mbit (1M words 16 bit) Static RAM Features Functional Description High speed The CY7C1061GN/CY7C10612GN is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits. t = 10 ns/15 ns AA To write to the device, take Chip Enables (CE LOW and CE 1 2 Low active power HIGH) and Write Enable (WE) input LOW. If Byte Low Enable I = 90 mA at 100 MHz CC (BLE) is LOW, then data from I/O pins (I/O through I/O ), is 0 7 Low CMOS standby current written into the location specified on the address pins (A through 0 A ). If Byte High Enable (BHE) is LOW, then data from I/O pins I = 20 mA (typ) 19 SB2 (I/O through I/O ) is written into the location specified on the 8 15 Operating voltages of 2.2 V to 3.6 V address pins (A through A ). 0 19 1.0 V data retention To read from the device, take Chip Enables (CE LOW and CE 1 2 HIGH) and Output Enable (OE) LOW while forcing the Write Automatic power down when deselected Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears TTL compatible inputs and outputs on I/O to I/O . If Byte High Enable (BHE) is LOW, then data from 0 7 Easy memory expansion with CE and CE features 1 2 memory appears on I/O to I/O . See Truth Table on page 13 8 15 for a complete description of Read and Write modes. Available in Pb-free 48-pin TSOP I, 54-pin TSOP II, and 48-ball VFBGA packages The input or output pins (I/O through I/O ) are placed in a high 0 15 impedance state when the device is deselected (CE HIGH/CE 1 2 Offered in dual Chip Enable options LOW), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE 1 LOW, CE HIGH, and WE LOW). 2 Logic Block Diagram INPUT BUFFER A 0 A 1 A 2 A 3 I/O I/O 1M x 16 0 7 A 4 ARRAY A 5 I/O I/O 8 15 A 6 A 7 A 8 A 9 COLUMN DECODER BHE WE CE 2 CE 1 OE BLE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-93680 Rev. *C Revised September 29, 2016 ROW DECODER A 10 A 11 A12 A 13 A 14 A15 A16 A 17 A 18 A 19 SENSE AMPSCY7C1061GN/CY7C10612GN Contents Selection Guide ................................................................3 Ordering Information ...................................................... 14 Pin Configurations ...........................................................3 Ordering Code Definitions ......................................... 14 Maximum Ratings .............................................................6 Package Diagrams .......................................................... 15 Operating Range ...............................................................6 Acronyms ........................................................................18 DC Electrical Characteristics ..........................................6 Document Conventions ................................................. 18 Capacitance ......................................................................7 Units of Measure ....................................................... 18 Thermal Resistance ..........................................................7 Document History Page ................................................. 19 AC Test Loads and Waveforms .......................................7 Sales, Solutions, and Legal Information ...................... 21 Data Retention Characteristics .......................................8 Worldwide Sales and Design Support ....................... 21 Over the Operating Range ...............................................8 Products ....................................................................21 Data Retention Waveform ................................................8 PSoCSolutions .......................................................21 AC Switching Characteristics .........................................9 Cypress Developer Community ................................. 21 Switching Waveforms ....................................................10 Technical Support ..................................................... 21 Truth Table ......................................................................13 Document Number: 001-93680 Rev. *C Page 2 of 21

Tariff Desc

8542.32.00 31 No ..Random Access Memory (RAM) including Single Inline Memory Modules (SIMMS), Dual Inline Memory Modules (DIMMS), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SD RAM), Rambus Dynamic Random Access Memory (RD RAM) and other similar memory
CYP
Cypress
Cypress / Spansion
CYPRESS SEMI
Cypress Semicon
Cypress Semiconductor
Cypress Semiconductor Corp
INF
INFINEON
Infineon IR
INFINEON (CYPRESS)
Infineon (IRF)
Infineon / Cypress
Infineon / IR
INFINEON TECH ICs
Infineon Technologies
INFINEON TECHNOLOGIES AG
Infineon Technologies Americas Corp.
Infinite Power Solutions
INTERNATIONAL RECTIF
INTERNATIONAL RECTIFIER
International Rectifier HiRel Products
INTL RECTIFIER
IR
IRH
Ramtron
Ramtron / Cypress Semiconductor
Ramtron International Corp
SP9
SPANSION

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