Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY621472E30 MoBL 4-Mbit (256K 16) Static RAM 4-Mbit (256K 16) Static RAM reduces power consumption when addresses are not toggling. Features Placing the device into standby mode reduces power consumption by more than 99 percent when deselected (CE Very high speed: 45 ns 1 HIGH or CE LOW or both BLE and BHE are HIGH). The input 2 Temperature range and output pins (I/O through I/O ) are placed in a high 0 15 Industrial: 40 C to +85 C impedance state when: Wide voltage range: 2.20 V to 3.60 V Deselected (CE HIGH or CE LOW) 1 2 Ultra low standby power Outputs are disabled (OE HIGH) Typical standby current: 2.5 A Maximum standby current: 7 A (Industrial) Both Byte High Enable and Byte Low Enable are disabled Ultra low active power (BHE, BLE HIGH) Typical active current: 3.5 mA at f = 1 MHz Write operation is active (CE LOW and CE HIGH and WE 1 2 Easy memory expansion with CE , CE , and OE Features 1 2 LOW) Automatic power down when deselected To write to the device, take Chip Enable (CE LOW and CE 1 2 HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable Complementary metal oxide semiconductor (CMOS) for (BLE) is LOW, then data from I/O pins (I/O through I/O ) is 0 7 optimum speed and power written into the location specified on the address pins (A through 0 A ). If Byte High Enable (BHE) is LOW, then data from I/O pins Available in Pb-free 44-pin thin small outline package 17 (I/O through I/O ) is written into the location specified on the (TSOP) II package 8 15 address pins (A through A ). 0 17 Byte power down feature To read from the device, take Chip Enable (CE LOW and CE 1 2 HIGH and Output Enable (OE) LOW while forcing the Write Functional Description Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear The CY621472E30 is a high performance CMOS static RAM on I/O to I/O . If Byte High Enable (BHE) is LOW, then data from (SRAM) organized as 256K words by 16 bits. This device 0 7 memory appears on I/O to I/O . See the Truth Table on page features advanced circuit design to provide ultra low active 8 15 11 for a complete description of read and write modes. current. It is ideal for providing More Battery Life (MoBL ) in portable applications such as cellular telephones. The device For a complete list of related documentation, click here. also has an automatic power down feature that significantly Logic Block Diagram DATA IN DRIVERS A 10 A 9 A 8 A 7 A 6 256K x 16 A 5 I/O I/O 0 7 A RAM Array 4 A 3 I/O I/O 8 15 A 2 A 1 A 0 COLUMN DECODER BHE CE POWER DOWN WE BHE CIRCUIT CE 1 BLE CE 2 OE BLE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-67798 Rev. *G Revised June 26, 2020 ROW DECODER A 11 A 12 A 13 A 14 A 15 A 16 A 17 SENSE AMPS