Product Information

CY62138FV30LL-45ZAXIT

CY62138FV30LL-45ZAXIT electronic component of Infineon

Datasheet
SRAM Chip Async Single 2.5V/3.3V 2M-bit 256K x 8 45ns 32-Pin STSOP-I T/R

Manufacturer: Infineon
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (AUD)

1: AUD 10.58 ( AUD 11.64 Inc GST) ea
Line Total: AUD 10.58 ( AUD 11.64 Inc GST)

1452 - Global Stock
Ships to you between
Fri. 26 Jul to Tue. 30 Jul
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
1452 - Global Stock


Ships to you between Fri. 26 Jul to Tue. 30 Jul

MOQ : 1
Multiples : 1
1 : AUD 10.58
10 : AUD 9.6777
100 : AUD 8.7754
250 : AUD 8.74
500 : AUD 8.3331
1000 : AUD 7.9792
1500 : AUD 7.4131

     
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RoHS - XON
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CY62138FV30 MoBL 2-Mbit (256 K 8) Static RAM 2-Mbit (256 K 8) Static RAM Features Functional Description Very high-speed: 45 ns The CY62138FV30 is a high performance CMOS static RAM organized as 256K words by 8 bits. This device features Temperature ranges advanced circuit design to provide ultra low active current. This Industrial: 40 C to 85 C is ideal for providing More Battery Life (MoBL ) in portable Automotive-A: 40 C to 85 C applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power Wide voltage range: 2.20 V to 3.60 V consumption. Place the device into standby mode reducing Pin compatible with CY62138CV25/30/33 power consumption when deselected (CE HIGH or CE LOW). 1 2 To write to the device, take Chip Enable (CE LOW and CE Ultra low standby power 1 2 HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O Typical standby current: 1 A pins (I/O through I/O ) is then written into the location specified 0 7 Maximum standby current: 5 A on the address pins (A through A ). 0 17 Ultra low active power To read from the device, take Chip Enable (CE LOW and CE 1 2 Typical active current: 1.6 mA at f = 1 MHz HIGH) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory Easy memory expansion with CE , CE , and OE Features 1 2 location specified by the address pins appear on the I/O pins. Automatic power down when deselected The eight input and output pins (I/O through I/O ) are placed in 0 7 a high impedance state when the device is deselected (CE Complementary metal oxide semiconductor (CMOS) for 1 HIGH or CE LOW), the outputs are disabled (OE HIGH), or Optimum speed and power 2 during a write operation (CE LOW and CE HIGH and WE 1 2 Offered in Pb-free 36-ball VFBGA, 32-pin TSOP II, 32-pin LOW). SOIC, 32-pin TSOP I and 32-pin STSOP packages Logic Block Diagram Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-08029 Rev. *M Revised August 19, 2013 CY62138FV30 MoBL Contents Pin Configurations ...........................................................3 Ordering Information ...................................................... 11 Product Portfolio ..............................................................3 Ordering Code Definitions ......................................... 11 Maximum Ratings .............................................................4 Package Diagrams .......................................................... 12 Operating Range ...............................................................4 Acronyms ........................................................................17 Electrical Characteristics .................................................4 Document Conventions ................................................. 17 Capacitance ......................................................................5 Units of Measure ....................................................... 17 Thermal Resistance ..........................................................5 Document History Page ................................................. 18 AC Test Loads and Waveforms .......................................5 Sales, Solutions, and Legal Information ...................... 19 Data Retention Characteristics .......................................6 Worldwide Sales and Design Support ....................... 19 Data Retention Waveform ................................................6 Products ....................................................................19 Switching Characteristics ................................................7 PSoC Solutions ...................................................... 19 Switching Waveforms ......................................................8 Cypress Developer Community ................................. 19 Truth Table ......................................................................10 Technical Support ..................................................... 19 Document Number: 001-08029 Rev. *M Page 2 of 19

Tariff Desc

8542.32.00 31 No ..Random Access Memory (RAM) including Single Inline Memory Modules (SIMMS), Dual Inline Memory Modules (DIMMS), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SD RAM), Rambus Dynamic Random Access Memory (RD RAM) and other similar memory
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