Ultra37000 CPLD Family 5V and 3.3V ISR High Performance CPLDs Features General Description In-System Reprogrammable (ISR) CMOS CPLDs The Ultra37000 family of CMOS CPLDs provides a range of high density programmable logic solutions with unparalleled JTAG interface for reconfigurability system performance. The Ultra37000 family is designed to bring Design changes do not cause pinout changes the flexibility, ease of use, and performance of the 22V10 to high Design changes do not cause timing changes density CPLDs. The architecture is based on a number of logic High Density blocks that are connected by a Programmable Interconnect Matrix (PIM). Each logic block features its own product term 32 to 512 macrocells array, product term allocator, and 16 macrocells. The PIM 32 to 264 I/O pins distributes signals from the logic block outputs and all input pins 5 dedicated inputs including 4 clock pins to the logic block inputs. Simple Timing Model All the Ultra37000 devices are electrically erasable and No fanout delays In-System Reprogrammable (ISR), which simplifies both design No expander delays and manufacturing flows, thereby reducing costs. The ISR No dedicated vs. I/O pin delays feature provides the ability to reconfigure the devices without No additional delay through PIM having design changes cause pinout or timing changes. The No penalty for using full 16 product terms Cypress ISR function is implemented through a JTAG-compliant serial interface. Data is shifted in and out through the TDI and No delay for steering or sharing product terms TDO pins, respectively. Because of the superior routability and 3.3V and 5V Versions simple timing model of the Ultra37000 devices, ISR allows users 1 to change existing logic designs while simultaneously fixing PCI Compatible pinout assignments and maintaining system performance. Programmable Bus-hold Capabilities on All I/Os The entire family features JTAG for ISR and boundary scan, and Intelligent Product Term Allocator Provides is compatible with the PCI Local Bus specification, meeting the electrical and timing requirements. The Ultra37000 family 0 to 16 product terms to any macrocell features user programmable bus-hold capabilities on all I/Os. Product term steering on an individual basis Product term sharing among local macrocells Ultra37000 5V Devices Flexible Clocking The Ultra37000 devices operate with a 5V supply and can 4 synchronous clocks per device support 5V or 3.3V I/O levels. V connections provide the CCO Product term clocking capability of interfacing to either a 5V or 3.3V bus. By connecting Clock polarity control per logic block the V pins to 5V the user insures 5V TTL levels on the CCO outputs. If V is connected to 3.3V the output levels meet 3.3V CCO Consistent Package and Pinout Offering across All JEDEC standard CMOS levels and are 5V tolerant. These Densities devices require 5V ISR programming. Simplifies design migration Same pinout for 3.3V and 5V devices Ultra37000V 3.3V Devices Packages Devices operating with a 3.3V supply require 3.3V on all V CCO pins, reducing the devices power consumption. These devices 44 to 256 Pins in PLCC, PQFP, TQFP, and Fine-Pitch BGA support 3.3V JEDEC standard CMOS output levels, and are Packages 5V-tolerant. These devices allow 3.3V ISR programming. Pb-free packages available Note 1. Due to the 5V tolerant nature of 3.3V device I/Os, the I/Os are not clamped to V , PCI V = 2V. CC IH Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number : 38-03007 Rev. *G Revised March 19, 2010 + Feedback Ultra37000 CPLD Family Contents Features .............................................................................1 Inductance........................................................................ 14 General Description .........................................................1 Capacitance ..................................................................... 14 Ultra37000 5V Devices ................................................1 Endurance Characteristics............................................. 14 Ultra37000V 3.3V Devices ..........................................1 3.3V Device Maximum Ratings ...................................... 14 Contents ............................................................................2 Operating Range.............................................................. 14 Selection Guide ................................................................3 3.3V Device Electrical Characteristics Over the Operating 5V Selection Guide ......................................................3 Range ............................................................................... 14 3.3V Selection Guide ...................................................3 Inductance........................................................................ 15 Architecture Overview of Ultra37000 Family .................4 Capacitance ..................................................................... 15 Programmable Interconnect Matrix .............................4 Endurance Characteristics............................................. 15 Logic Block ..................................................................4 AC Characteristics ......................................................... 15 Product Term Allocator ................................................5 Switching Characteristics Over the Operating Range .. 16 Ultra37000 Macrocell ..................................................5 Switching Characteristics Over the Operating Range .. 18 Clocking .......................................................................7 Switching Waveforms .................................................... 19 Timing Model ...............................................................7 Power Consumption ....................................................... 23 JTAG and PCI Standards .................................................8 Typical 5V Power Consumption ................................ 23 PCI Compliance ..........................................................8 Typical 3.3V Power Consumption ............................. 26 IEEE 1149.1-compliant JTAG .....................................8 Pin Configurations .......................................................... 29 Development Software Support ......................................8 Ordering Information ...................................................... 34 Warp ............................................................................8 5V Ordering Information ................................................ 34 Warp Professional ...................................................8 3.3V Ordering Information ............................................. 35 Warp Enterprise .......................................................8 Addendum .......................................................................35 Third-Party Software ...................................................8 3.3V Operating Range ............................................... 35 Programming ...............................................................8 Package Diagrams .......................................................... 36 Third-Party Programmers ............................................9 Document History Page ................................................. 40 Logic Block Diagrams ....................................................10 Sales, Solutions, and Legal Information ...................... 43 5V Device Maximum Ratings .........................................13 Worldwide Sales and Design Support ....................... 43 Operating Range..............................................................13 Products ....................................................................43 5V Device Electrical Characteristics Over the Operating PSoC Solutions ......................................................... 43 Range ...............................................................................13 Document Number : 38-03007 Rev. *G Page 2 of 43 + Feedback