CY2XP31 312.5 MHz LVPECL Clock Generator Features Functional Description One LVPECL output pair The CY2XP31 is a PLL (Phase Locked Loop) based high performance clock generator. It is optimized to generate 10 Gb Output frequency: 312.5 MHz Ethernet, SONET, and other high performance clock frequencies. It also produces an output frequency that is 12.5 External crystal frequency: 25 MHz times the crystal frequency. It uses Cypresss low noise VCO Low RMS phase jitter at 312.5 MHz, using 25 MHz crystal technology to achieve less than 1 ps typical RMS phase jitter, (1.875 MHz to 20 MHz): 0.3 ps (typical) which meets both 10 Gb Ethernet and SONET jitter requirements. The CY2XP31 has a crystal oscillator interface Pb-free 8-Pin TSSOP package input and one LVPECL output pair. Supply voltage: 3.3 V or 2.5 V Commercial and industrial temperature ranges Logic Block Diagram XIN CLK External CRYSTAL PHASE VCO /2 Crystal OSCILLATOR DETECTOR CLK XOUT /25 OE Pinouts Figure 1. Pin Diagram 8-Pin TSSOP VDD 1 8 VDD VSS 2 7 CLK XOUT36 CLK XIN45 OE Table 1. Pin Definition 8-Pin TSSOP Pin Number Pin Name I/O Type Description 1, 8 VDD Power 3.3 V or 2.5 V power supply. All supply current flows through pin 1 2 VSS Power Ground 3, 4 XOUT, XIN XTAL Output and Input Parallel resonant crystal interface 5 OE CMOS Input Output enable. When HIGH, the output is enabled. When LOW, the output is high impedance 6,7 CLK , CLK LVPECL Output Differential clock output Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document : 001-06385 Rev. *H Revised April 7, 2011 + Feedback CY2XP31 Frequency Table Inputs Output Frequency (MHz) Crystal Frequency (MHz) PLL Multiplier Value 25 12.5 312.5 Absolute Maximum Conditions Parameter Description Conditions Min Max Unit V Supply Voltage 0.5 4.4 V DD 1 V Input Voltage, DC Relative to V 0.5 V + 0.5 V IN SS DD T Temperature, Storage Non operating 65 150 C S T Temperature, Junction 135 C J ESD ESD Protection, Human Body Model JEDEC STD 22-A114-B 2000 V HBM UL94 Flammability Rating At 1/8 in. V0 2 Thermal Resistance, Junction to Ambient 0 m/s airflow 100 C/W JA 1 m/s airflow 91 2.5 m/s airflow 87 Operating Conditions Parameter Description Min Max Unit V 3.3 V Supply Voltage 3.135 3.465 V DD 2.5 V Supply Voltage 2.375 2.625 V T Ambient Temperature, Commercial 0 70 C A Ambient Temperature, Industrial 40 85 C T Power-up time for all V to reach minimum specified voltage (ensure power ramps 0.05 500 ms PU DD is monotonic) Notes 1. The voltage on any input or I/O pin cannot exceed the power pin during power-up. 2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model. Document : 001-06385 Rev. *H Page 2 of 10 + Feedback