Product Information

CY29948AXC

CY29948AXC electronic component of Infineon

Datasheet
Clock Drivers & Distribution 2.5V or /3.3V 200MHz COM

Manufacturer: Infineon
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (AUD)

1: AUD 24.0969 ( AUD 26.51 Inc GST) ea
Line Total: AUD 24.0969 ( AUD 26.51 Inc GST)

242 - Global Stock
Ships to you between
Thu. 18 Jul to Mon. 22 Jul
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
242 - Global Stock


Ships to you between Thu. 18 Jul to Mon. 22 Jul

MOQ : 1
Multiples : 1

Stock Image

CY29948AXC
Infineon

1 : AUD 24.0969
10 : AUD 22.3985
25 : AUD 21.4785
100 : AUD 20.2046
250 : AUD 17.6392
500 : AUD 17.5685
1000 : AUD 16.79
2500 : AUD 16.6838
5000 : AUD 16.1708

     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Brand
Number Of Outputs
Propagation Delay - Max
Mounting
Package Type
Number Of Clock Inputs
Signal Type
Operating Temperature Classification
Output Frequency
Operating Supply Voltage Typ
Operating Supply Voltage Max
Duty Cycle
Input Frequency
Operating Temp Range
Pin Count
Quiescent Current
Type
Output Logic Level
Rad Hardened
Operating Supply Voltage Min
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Notes:- Show Stocked Products With Similar Attributes.

CY29948 2.5 V or 3.3 V, 200 MHz, 1:12 Clock Distribution Buffer 2.5 V or 3.3 V, 200 MHz, 1:12 Clock Distribution Buffer Features Functional Description 2.5 V or 3.3 V operation The CY29948 is a low-voltage 200 MHz clock distribution buffer with the capability to select either a differential LVPECL or a 200 MHz clock support LVCMOS/LVTTL compatible input clock. The two clock sources can be used to provide for a test clock as well as the primary LVPECL or LVCMOS/LVTTL clock input system clock. All other control inputs are LVCMOS/LVTTL LVCMOS-/LVTTL-compatible inputs compatible. The 12 outputs are LVCMOS or LVTTL compatible and can drive 50 series or parallel terminated transmission 12 clock outputs: drive up to 24 clock lines lines. For series terminated transmission lines, each output can Synchronous Output Enable drive one or two traces giving the device an effective fanout of 1:24. The outputs can also be three-stated via the three-state Output three-state control input TS#. Low output-to-output skews make the CY29948 an ideal clock distribution buffer for nested clock trees in the most 150 ps typical output-to-output skew demanding of synchronous systems. Pin compatible with MPC948, MPC948L, MPC9448 The CY29948 also provides a synchronous output enable input Available in Commercial and Industrial temp. range for enabling or disabling the output clocks. Since this input is internally synchronized to the input clock, potential output 32-pin TQFP package glitching or runt pulse generation is eliminated. For a complete list of related documentation, click here. Block Diagram VDD VDDC PECL_CLK 0 PECL_CLK# 12 Q0-Q11 TCLK 1 TCLK_SEL SYNC_OE TS# Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-07288 Rev. *J Revised April 17, 2018CY29948 Contents Pin Configuration .............................................................3 Acronyms ........................................................................ 11 Pin Description .................................................................3 Document Conventions ................................................. 11 Output Enable/Disable .....................................................4 Units of Measure ....................................................... 11 Maximum Ratings .............................................................5 Document Revision History ........................................... 12 DC Parameters ..................................................................5 Sales, Solutions, and Legal Information ...................... 13 Thermal Resistance ..........................................................6 Worldwide Sales and Design Support ....................... 13 AC Parameters ..................................................................6 Products .................................................................... 13 Ordering Information ........................................................9 PSoC Solutions ...................................................... 13 Ordering Code Definitions ...........................................9 Cypress Developer Community ................................. 13 Package Diagrams ..........................................................10 Technical Support ..................................................... 13 Document Number: 38-07288 Rev. *J Page 2 of 13

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
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