CY22381 CY223811 Three-PLL General Purpose FLASH Programmable Clock Generator Improves frequency accuracy over temperature, age, process, Features and initial offset Three integrated phase-locked loops Non-volatile programming enables easy customization, ultra-fast turnaround, performance tweaking, design timing Ultra-wide divide counters (eight-bit Q, eleven-bit P, and margin testing, inventory control, lower part count, and more seven-bit post divide) secure product supply. Can also be programmed multiple times Improved linear crystal load capacitors which reduces programming errors and provides an easy upgrade path for existing designs Flash programmability In-house programming of samples and prototype quantities is Field programmability available using the CY3672 FTG development Kit. Production Low-jitter, high-accuracy outputs quantities are available through Cypresss value-added distribution partners or by using third party programmers from Power-management options (Shutdown, OE, Suspend) BP Microsystems, HiLo Systems, and others. Configurable crystal drive strength Performance suitable for high-end multimedia, communications, industrial, A/D converters, and consumer Frequency select option through external LVTTL Input applications 3.3V operation Supports numerous low-power application schemes and 8-pin SOIC package (CY22381) reduces EMI by allowing unused outputs to be turned off 8-pin SOIC package with NiPdAu lead finish (CY223811) Adjust crystal drive strength for compatibility with virtually all crystals CyClocks RT support External frequency select option for PLL1, CLKA, and CLKB Benefits Industry standard supply voltage Generates up to three unique frequencies on three outputs up Industry standard packaging saves on board space to 200 MHz from an external source. Functional upgrade for current CY2081 family. Easy-to-use software support for design entry Allows for 0 ppm frequency generation and frequency conversion under the most demanding applications Logic Block Diagram XTALIN OSC. XTALOUT PLL1 Divider CLKC 11-BIT P 7-BIT CONFIGURATION 8-BIT Q FLASH 4 3 PLL2 Crosspoint Divider 11-BIT P CLKB SHUTDOWN/OE Switch 7-BIT 8-BIT Q FS/SUSPEND PLL3 Divider 11-BIT P CLKA 7-BIT 8-BIT Q Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document : 38-07012 Rev. *F Revised December 11, 2008 + Feedback CY22381 CY223811 Pinouts Figure 1. CY22381, CY223811- 8-pin SOIC CLKC 1 8 FS/SUSPEND/OE/SHUTDOWN GND 2 7 V DD XTALIN 3 6 CLKA XTALOUT 4 5 CLKB Pin Definitions Name Pin Number Description CLKC 1 Configurable clock output C GND 2 Ground XTALIN 3 Reference crystal input or external reference clock input XTALOUT 4 Reference crystal feedback (float if XTALIN is driven by external reference clock) CLKB 5 Configurable clock output B CLKA 6 Configurable clock output A V 7 Power supply DD FS/SUSPEND/ 8 General Purpose Input. Can be Frequency Control, Suspend mode control, Output OE/SHUTDOWN Enable, or full-chip shutdown. of PLL1, the output divider of CLKB, and the output divider of Operation CLKA. Any divider change as a result of switching the FS input is guaranteed to be glitch free. The CY22381 is an upgrade to the existing CY2081. The new device has a wider frequency range, greater flexibility, improved The general-purpose input can simultaneously control the performance, and incorporates many features that reduce PLL Suspend feature, turning off a set of PLLs and outputs sensitivity to external system issues. determined during programming. The device has three PLLs that allow each output to operate at When programmed as an Output Enable (OE) the input forces an independent frequencies. These three PLLs are completely all outputs to be placed in a three-state condition when LOW. programmable. When programmed as a Shutdown, the input forces a full chip The CY223811 is the CY22381 with NiPdAu lead finish. shutdown mode when LOW. Configurable PLLs Crystal Input PLL1 generates a frequency that is equal to the reference The input crystal oscillator is an important feature of this device divided by an eight-bit divider (Q) and multiplied by an 11-bit because of its flexibility and performance features. divider in the PLL feedback loop (P). The output of PLL1 is sent The oscillator inverter has programmable drive strength. This to the crosspoint switch. The frequency of PLL1 can optionally allows for maximum compatibility with crystals from various be changed by using the external CMOS general purpose input. manufacturers, processes, performances, and qualities. See the following section on General-Purpose Input for more detail. The input load capacitors are placed on-die to reduce external component cost. These capacitors are true parallel-plate PLL2 generates a frequency that is equal to the reference capacitors for ultra-linear performance. These were chosen to divided by an eight-bit divider (Q) and multiplied by an 11-bit reduce the frequency shift that occurs when non-linear load divider in the PLL feedback loop (P). The output of PLL2 is sent capacitance interacts with load, bias, supply, and temperature to the crosspoint switch. changes. Non-linear (FET gate) crystal load capacitors must not PLL3 generates a frequency that is equal to the reference be used for MPEG, POTS dial tone, communications, or other divided by an eight-bit divider (Q) and multiplied by an 11-bit applications that are sensitive to absolute frequency divider in the PLL feedback loop (P). The output of PLL3 is sent requirements to the cross-point switch. The value of the load capacitors is determined by six bits in a programmable register. The load capacitance can be set with a General-Purpose Input resolution of 0.375pF for a total crystal load range of 6pF to 30pF. The CY22381 features an output control pin (pin 8) that can be For driven clock inputs the input load capacitors may be programmed to control one of four features. completely bypassed. This enables the clock chip to accept When programmed as a Frequency Select (FS), the input can driven frequency inputs up to 166 MHz. If the application requires select between two arbitrarily programmed frequency settings. a driven input, then XTALOUT must be left floating. The Frequency Select can change the following the frequency Document : 38-07012 Rev. *F Page 2 of 9 + Feedback