Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY14C512Q CY14B512Q CY14E512Q 512-Kbit (64K 8) SPI nvSRAM 512-Kbit (64K 8) SPI nvSRAM Industry standard configurations Features Operating voltages: 512-Kbit nonvolatile static random access memory (nvSRAM) CY14C512Q: V = 2.4 V to 2.6 V CC internally organized as 64K 8 CY14B512Q: V = 2.7 V to 3.6 V CC STORE to QuantumTrap nonvolatile elements initiated CY14E512Q: V = 4.5 V to 5.5 V CC automatically on power-down (AutoStore) or by using SPI Industrial temperature instruction (Software STORE) or HSB pin (Hardware 8- and 16-pin small outline integrated circuit (SOIC) package STORE) Restriction of hazardous substances (RoHS) compliant RECALL to SRAM initiated on power-up (Power-Up RECALL) or by SPI instruction (Software RECALL) Functional Description Support automatic STORE on power-down with a small capacitor (except for CY14X512Q1A) 1 The Cypress CY14X512Q combines a 512-Kbit nvSRAM with High reliability a nonvolatile element in each memory cell with serial SPI interface. The memory is organized as 64 K words of 8 bits each. Infinite read, write, and RECALL cycles The embedded nonvolatile elements incorporate the 1million STORE cycles to QuantumTrap QuantumTrap technology, creating the worlds most reliable Data retention: 20 years at 85 C nonvolatile memory. The SRAM provides infinite read and write 40-MHz, and 104-MHz High-speed serial peripheral interface cycles, while the QuantumTrap cells provide highly reliable (SPI) nonvolatile storage of data. Data transfers from SRAM to the 40-MHz clock rate SPI write and read with zero cycle delay nonvolatile elements (STORE operation) takes place automati- 104-MHz clock rate SPI write and SPI read (with special fast cally at power-down (except for CY14X512Q1A). On power-up, read instructions) data is restored to the SRAM from the nonvolatile memory Supports SPI mode 0 (0, 0) and mode 3 (1, 1) (RECALL operation). You can also initiate the STORE and RECALL operations through SPI instruction SPI access to special functions Nonvolatile STORE/RECALL For a complete list of related documentation, click here. 8-byte serial number Configuration Manufacturer ID and Product ID Sleep mode Feature CY14X512Q1A CY14X512Q2A CY14X512Q3A Write protection AutoStore No Yes Yes Hardware protection using Write Protect (WP) pin Software Yes Yes Yes Software protection using Write Disable instruction STORE Software block protection for 1/4, 1/2, or entire array Hardware No No Yes Low power consumption STORE Average active current of 3 mA at 40 MHz operation Average standby mode current of 150 A Sleep mode current of 8 A Logic Block Diagram V V CC CAP Serial Number 8 x 8 Power Control Manufacturer ID / Block Product ID QuantumTrap 64 K x 8 SLEEP STORE SRAM RDSN/WRSN/RDID SI Memory 64 K x 8 RECALL Data & READ/WRITE CS SPI Control Logic Address STORE/RECALL/ASENB/ASDISB SCK Write Protection Control Instruction decoder WP SO WRSR/RDSR/WREN Status Register Note 1. This device will be referred to as nvSRAM throughout the document. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-65267 Rev. *I Revised January 30, 2018