MB9BD10T Series 32-bit ARM Cortex -M3 FM3 Microcontroller The MB9BD10T Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and competitive cost. These series are based on the ARM Cortex -M3 Processor with on-chip Flash memory and SRAM, and has peripheral functions 2 such as Motor Control Timers, ADCs, and Communication Interfaces (USB, CAN, UART, CSIO, I C, LIN, Ethernet-MAC). The products which are described in this datasheet are placed into TYPE 2 product categories inFM3 Family Peripheral Manua. Features USB device 32-bit ARM Cortex -M3 Core USB2.0 Full-Speed supported Processor version: r2p1 Max 6 EndPoint supported Up to 144 MHz Frequency Operation EndPoint 0 is control transfer EndPoint 1, 2 can be selected Bulk-transfer, Memory Protection Unit (MPU): improves the reliability of an Interrupt-transfer or Isochronous-transfer embedded system EndPoint 3 to 5 can be selected Bulk-transfer or Integrated Nested Vectored Interrupt Controller (NVIC): Interrupt-transfer 1 NMI (non-maskable interrupt) and 48 peripheral interrupts EndPoint 1 to 5 is comprised Double Buffers and 16 priority levels Endpoint 0, 2 to 5: 64 bytes 24-bit System timer (Sys Tick): System timer for OS task Endpoint 1: 256 bytes management USB host On-chip Memories USB2.0 Full/Low-speed supported Bulk-transfer, interrupt-transfer and Isochronous-transfer Flash memory support Up to 1 MB USB Device connected/dis-connected automatically detect Built-in Flash Accelerator System with 16 KB trace buffer IN/OUT token handshake packet automatically memory Max 256-byte packet-length supported The read access to Flash memory can be achieved without wait cycle up to operation frequency of 72 MHz. Even at the Wake-up function supported operation frequency more than 72 MHz, an equivalent access to Flash memory can be obtained by Flash CAN Interface (Max 2 channels) Accelerator System. Compatible with CAN Specification 2.0A/B Security function for code protection Maximum transfer rate: 1 Mbps SRAM Built-in 32 message buffer This Series contain a total of up to 128 KB on-chip SRAM. This is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Ethernet - MAC (Max 2 channels) Cortex-M3 core. SRAM1 is connected to System bus. Compliant with IEEE802.3 specification SRAM0: Up to 64 KB 10 Mbps / 100 Mbps data transfer rates supported SRAM1: Up to 64 KB MII/RMII for external PHY device supported. MII: Max 1 channel USB Interface (Max 2 channels) RMII: Max 2 channels USB interface is composed of Device and Host. Full-Duplex and Half-Duplex mode supported. PLL for USB/Ethernet is built-in, USB clock or Ethernet clock can be generated by multiplication of Main clock. Wake-ON-LAN supported Built-in dedicated descriptor-system DMAC Built-in 2 KB Transmit FIFO and 2 KB Receive FIFO. Compliant IEEE1558-2008 (PTP) PLL for USB/Ethernet is built-in, USB clock or Ethernet clock can be generated by multiplication of Main clock. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-05629 Rev.*B Revised March 9, 2017 MB9BD10T Series Multi-function Serial Interface (Max 8 channels) DMA Controller (8 channels) DMA Controller has an independent bus for CPU, so CPU and 4 channels with 16 steps 9-bit FIFO (ch.4 to ch.7), DMA Controller can process simultaneously. 4 channels without FIFO (ch.0 to ch.3) 8 independently configured and operated channels Operation mode is selectable from the followings for each channel. Transfer can be started by software or request from the built-in peripherals UART CSIO Transfer address area: 32-bit (4 GB) LIN 2 Transfer mode: Block transfer/Burst transfer/Demand I C transfer UART Transfer data type: byte/half-word/word Full duplex double buffer Transfer block count: 1 to 16 Selection with or without parity supported Number of transfers: 1 to 65536 Built-in dedicated baud rate generator A/D Converter (Max 32 channels) External clock available as a serial clock 12-bit A/D Converter Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4) Successive Approximation Register type Various error detect functions available (parity errors, framing Built-in 3 unit errors, and overrun errors) Conversion time: 1.0 s 5 V CSIO Priority conversion available (priority at 2 levels) Full duplex double buffer Scanning conversion mode Built-in dedicated baud rate generator Built-in FIFO for conversion data storage (for SCAN Overrun error detect function available conversion: 16 steps, for Priority conversion: 4 steps) LIN LIN protocol Rev.2.1 supported Base Timer (Max 16 channels) Full duplex double buffer Operation mode is selectable from the followings for each channel. Master/Slave mode supported 16-bit PWM timer LIN break field generate (can be changed 13 to 16-bit length) 16-bit PPG timer LIN break delimiter generate (can be changed 1 to 4-bit length) 16-/32-bit reload timer Various error detect functions available (parity errors, framing 16-/32-bit PWC timer errors, and overrun errors) 2 Multi-function Timer (Max 3 units) I C The Multi-function timer is composed of the following blocks. Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported 16-bit free-run timer 3ch./unit Input capture 4ch./unit External Bus Interface Output compare 6ch./unit Supports SRAM, NOR and NAND Flash device A/D activation compare 3ch./unit Up to 8 chip selects Waveform generator 3ch./unit 8-/16-bit Data width 16-bit PPG timer 3ch./unit Up to 25-bit Address bit Maximum area size: Up to 256 MB Supports Address/Data multiplex Supports external RDY input Document Number: 002-05629 Rev.*B Page 2 of 133