PI6CX201A 25MHz Jitter Attenuator Features Description The PI6CX201A is composed of a phase-locked loop with PLL with quartz stabilized VCXO integrated VCXO oscillator for use in the clock jitter attenuation Optimized for 25MHz input/output frequency applications. It is optimized for use with a SaRonix-eCera Other frequencies available crystal of 25MHz, and has typical output phase jitter less than Low phase jitter less than 350fs typical 350fs (RMS). Free run mode 100ppm Single ended input and outputs 3.3V single supply Lock detection Industrial Temperature: 40C to 85C 20-pin TSSOP package Block Diagram Pin Configuration 1 20 External X1 X2 SaRonix-eCera xtal VC 2 19 AVDD Lock AGND 3 18 DGND Detector 4 17 LF Pre CLK OUT1 REF CLK CLK OUT1 Charge Divider PFD VCXO Pump S0 5 16 LD FB CLK S1 CLK OUT2 CLK OUT2 6 15 Divider S2 DVDD 7 14 FREE RUN DGND 8 13 DGND FB CLK 9 12 External Connection Required DVDD REF CLK 10 11 12-0150 PI6CX201A Rev. C 01/03/2012 1 S0 S1 S2 LD Free Run LF VC S0 S1 S2PI6CX201A 25MHz Jitter Attenuator Pin Descriptions for 20-pin TSSOP Package Pin Name Type Pin No Description XI I 1 Crystal input pin VC I 2 VCXO control voltage input LF I 4 Loop filter pin for external loop filter connection AGND PWR 3 Analog ground LVCMOS selection pins for internal CLK OUT2 divider, Pins S0, S1, S2 I 5, 6, 7 have internal pull up resistor REF CLK I 11 LVCMOS input clock signal to phase detector FB CLK I 12 LVCMOS feedback clock signal to phase detector DGND PWR 9, 13, 18 Digital ground DVDD PWR 10, 14 Digital power LVCMOS output clock of the internal VCXO with divider CLK OUT2 O 15 controlled by S0 and S1 LVCMOS lock detect output, LD output is logic 0 when REF CLKx is greater than 1MHz, and phase difference be- LD O 16 tween REF CLKx and FB CLK is more than 2ns for 8 con- secutive clock pulses. The clock pulse frequency is equal to the crystal frequency. CLK OUT1 O 17 LVCMOS output clock of the internal VCXO AVDD PWR 19 Analog power X2 O 20 Crystal output pin When FREE RUN is logic low, chip is infree ru mode. The output will remain fixed at a fixed frequency with up to FREE RUN I 8 a 100ppm offset from the nominal 25MHz. Logic HIGH is normal mode, with output locked to the input. Internal pull-up. Frequency Selection Table Input Frequency S0 S1 S2 Output Frequency 25MHz 1 0 1 25MHz 12.5MHz 0 0 1 25MHz 33.33MHz 0 1 1 25MHz 66.67MHz 1 1 1 25MHz PI6CX201A Rev. C 01/03/2012 12-0150 2