A product Line of Pb Diodes Incorporated Lead-free Green PI6CB18200 Very Low Power 2-Output PCIe Clock Buffer Features Description 1.8V supply voltage The PI6CB18200 is an 2-output very low power PCIe Gen1/ Gen2/Gen3/Gen4 clock buffer. It takes an reference input to HCSL input: 100MHz, also support 50MHz or 125MHz via fanout two 100MHz low power differential HCSL outputs. SMBus Individual OE pin for each output provides easier power 2 differential low power HCSL outputs management. Individual output enable It uses Diodes proprietary PLL design to achieve very low jit- Programmable Slew rate and output amplitude for each output ter that meets PCIe Gen1/Gen2/Gen3 requirements. Other Differential outputs blocked until PLL is locked than PCIe 100MHz support, this device also support Ethernet Strapping pins or SMBus for configuration application with 50MHz or 125MHz via SMBus. It provides vari- 3.3V tolerant SMBus interface support ous options such as different slew rate and amplitude through Very low jitter outputs strapping pins or SMBUS so that users can configure the device easily to get the optimized performance for their individual Differential cycle-to-cycle jitter <50ps boards. Differential output-to-output skew <50ps PCIe Gen1/Gen2/Gen3/ Gen4 compliant Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) Block Diagram Halogen and Antimony Free. Green Device (Note 3) OE 1:0 For automotive applications requiring specic cfi hange control (i.e. parts qualified to AEC-Q100/101/200, PPAP capable, and manufactured in IATF 16949 certified facilities), please Q1 IN+ contact us or your local Diodes representative. PLL IN- Q0 A product Line of Diodes Incorporated PI6CB18200 Pin Configuration 24 23 22 21 20 19 1 Q1- NC 18 V Q1+ DD R 2 17 3 VDDA IN+ 16 GND IN- 4 15 GNDA GND R 5 Q0- 14 Q0+ GND DIG 6 13 7 8 9 10 11 12 Pin Description Pin Number Pin Name Type Description 1, 24 NC Internal connected for feedback loop. Do not connect this pin 2 V R Power Power supply for input differential buffers DD 3 IN+ Input Differential true clock input 4 IN- Input Differential complementary clock input 5 GND R Power Ground for input differential buffers 6 GND DIG Power Ground for digital circuitry 7 V DIG Power Power supply for digital circuitry, nominal 1.8V DD 8 SCLK Input CMOS SMBUS clock input, 3.3V tolerant Input/ 9 SDATA CMOS SMBUS Data line, 3.3V tolerant Output 10, 21 GND Power Ground 11, 20 V Power Power supply for differential outputs DDO Active low input for enabling Q0 pair. This pin has an internal pull-down. 1 12 OE0 Input CMOS =disable outputs, 0 = enable outputs 13 Q0+ Output HCSL Differential true clock output 14 Q0- Output HCSL Differential complementary clock output 15 GNDA Power Ground for analog circuitry 16 V Power Power supply for analog circuitry DDA 17 Q1+ Output HCSL Differential true clock output 18 Q1- Output HCSL Differential complementary clock output Active low input for enabling Q1 pair. This pin has an internal pull-down. 1 19 OE1 Input CMOS =disable outputs, 0 = enable outputs Input notifies device to sample latched inputs and start up on first high asser - 22 PD Input CMOS tion. Low enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal pull-up resistor. Latch to select low loop bandwidth, bypass PLL, and high loop bandwidth. This 23 BW SEL TRI Input Tri-level pin has both internal pull-up and pull-down www.diodes.com June 2020 PI6CB18200 2 Diodes Incorporated Document Number DS40224 Rev 5-2 VDD DIG NC SCLK BW SEL TRI SDATA PD GND GND V DDO VDDO OE0 OE1