74HCT595T16-13

74HCT595 8-BIT SHIFT REGISTER WITH 8-BIT OUTPUT REGISTER Description Pin Assignments The 74HCT595 is an high speed CMOS device that is designed to be pin compatable with 74LS low power Schottky types. An eight bit shift register accpets data from the serial input (DS) on each positive transition of the shift register clock (STCP). When asserted low the reset function (MR) sets all shift register values to zero and is indepent of all clocks. Data from the input serial shift register is placed in the output register with a rising pulse on the storages resister clock (SHCP). With the output enable (OE asserted low the 3-state outputs Q0- Q7 become active and present th All registers capture data on rising edge and change output on the falling edge. If both clocks are connected together the input shift register is always one clock cycle ahead of the output register. Features Applications Supply Voltage Range from 4.5V to 5.5V General Purpose Logic Sinks or sources 8mA at V = 4.5V Serial to Parallel Data conversion CC CMOS low power consumption Capture and hold data for extended periods of time. Schmitt Trigger Action at All Inputs Allow simple serial bit streams from a microcontroller to control as many peripheral lines as needed. Inputs accept up to 6.0V Wide array of products such as: ESD Protection Tested per JESD 22 o Computer peripherals Exceeds 200-V Machine Model (A115-A) o Appliances Exceeds 2000-V Human Body Model (A114-A) o Industrial control Exceeds 1000-V Charged Device Model (C101C) Latch-Up Exceeds 250mA per JESD 78, Class II Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) Halogen and Antimony Free. Green Device (Note 3) Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant. 2. See 74HCT595 Pin Descriptions Functional Diagram Pin Number Pin Name Description 1 Q1 Parallel Data Output 1 2 Q2 Parallel Data Output 2 3 Q3 Parallel Data Output 3 4 Q4 Parallel Data Output 4 5 Q5 Parallel Data Output 5 6 Q6 Parallel Data Output 6 7 Q7 Parallel Data Output 7 8 GND Ground 9 Q7S Serial Data Output 10 MR Master Reset Input 11 SHCP Shift Register Clock Input 12 STCP Storage Register Clock Input 13 OE Output Enable Input 14 DS Serial Data Input 15 Q0 Parallel Data Output 0 16 Vcc Supply Voltage Logic Diagram STAGE 0 STAGES 1 TO 6 STAGE 7 DS DQ DQ DQ Q7S FF0 FF7 CP CP R R SHCP MR DQ DQ LATCH LATCH CP CP STCP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 of 11 July 2013 74HCT595 Diodes Incorporated www.diodes.com Document number: DS35493 Rev. 3 - 2 Preliminary