IP Lock Users Manual Design Gateway Co.,Ltd. Rev 1.8 (PD0601-6-01-08E) *** Please read this manual carefully before using IP Lock *** Revision History Revision Date Detail of change 1.0 10-May-06 Initial Release 1.1 01-Aug-06 Adding IP lock core for Altera FPGA. 1.2 14-Nov-06 Update detail of setting internal pull-up on ISE Update detail of SC0 signal 1.3 08-Nov-07 Support Xilinx Virtex5 Adding Troubleshooting 1.4 30-Dec-09 Update resource usage on Xilinx 1.5 06-Aug-10 Update Figure 4-1 and 4-8 1.6 15-Oct-10 Update Device support 1.7 18-Dec-18 Update How to install Device driver topic for window10 1.8 28-May-19 Add software installation IP Lock Users Manual - I - PD0601-6-01-06E