CMX909B CML Microcircuits GMSK COMMUNICATION SEMICONDUCTORS Packet Data Modem D/909B/2 November 2008 Features GMSK Modulation/Demodulation On-chip Packet Detection Rx or Tx up to 38.4kbits/sec Parallel Host Processor Interface Full and Short Data Packet Framing Low Power 3.0V/5.0V Operation Mobitex Compatible including Flexible Operating and Powersave R14N Short Block Frames Modes 1. Brief Description The CMX909B is a half-duplex Gaussian Minimum Shift Keyed (GMSK) BT=0.3 modem data pump with on-chip packet data handling. GMSK modulation optimises the data throughput for a given bandwidth RF channel and the on-chip packet data handling relieves the host C of regular processing tasks, such as maintaining Bit and Frame Synchronisation, Block Formatting, CRC and FEC Error Processing, Data Interleaving and Scrambling. The demodulator uses decision feedback equalisation techniques to reduce the channel distortion effects and enhance the receiver performance without the computational overhead of maximum likelihood (Viterbi) estimation methods. The CMX909B is pin, function and software backwards compatible with the FX909A and MX909A modems and also uses the same external components. It offers improved performance, higher data rates and lower voltage operation, as well as handling the recent R14N extension to Mobitex for short block frames. The CMX909B also offers 2-strength Xtal driver circuitry for wider choice of xtals, optional zero- error or one-error frame sync. detection, multiple powersave options for intelligent power management, and availability in both 24-pin TSSOP and SSOP low-height package options. The CMX909B is ideally suited to wireless data applications such as Mobitex terminals, wireless telemetry, licence-free radio data and ISM band radio schemes. 2008 CML Microsystems Plc GMSK Packet Data Modem CMX909B CONTENTS Section Page 1. Brief Description .................................................................................................1 1.1. History......................................................................................................4 2. Block Diagram.....................................................................................................5 3. Signal List ............................................................................................................6 4. External Components.........................................................................................8 5. General Description............................................................................................9 5.1. Description of Blocks ...............................................................................9 5.1.1. Data Bus Buffers.........................................................................9 5.1.2. Address and R/W Decode ..........................................................9 5.1.3. Status and Data Quality Registers..............................................9 5.1.4. Command, Mode and Control Registers ....................................9 5.1.5. Data Buffer................................................................................10 5.1.6. CRC Generator/Checker ..........................................................10 5.1.7. FEC Generator/Checker ...........................................................10 5.1.8. Interleave/De-interleave Buffer .................................................10 5.1.9. Frame Sync Detect ...................................................................10 5.1.10. Rx I/P Amp................................................................................10 5.1.11. Tx/Rx Low Pass Filter...............................................................10 5.1.12. Tx Output Buffer........................................................................10 5.1.13. Rx Level/Clock Extraction.........................................................12 5.1.14. Clock Oscillator and Dividers....................................................12 5.1.15. Scramble/De-scramble .............................................................12 5.2. Modem - C Interaction .........................................................................13 5.3. Data Formats .........................................................................................14 5.3.1. General Purpose Formats ........................................................14 5.3.2. Mobitex Frame Structure ..........................................................14 5.4. The Programmers View ........................................................................16 5.4.1. Data Buffer................................................................................16 5.4.2. Command Register...................................................................16 5.4.3. Control Register........................................................................27 5.4.4. Mode Register...........................................................................30 5.4.5. Status Register .........................................................................31 5.4.6. Data Quality Register................................................................33 5.5. CRC, FEC, Interleaving and Scrambling Information:...........................34 5.5.1. CRC 34 5.5.2. FEC 35 5.5.3. Interleaving ...............................................................................35 5.5.4. Scrambling ................................................................................36 6. Application Notes .............................................................................................37 6.1. Transmit Frame Example.......................................................................37 6.2. Receive Frame Example........................................................................39 6.3. Clock Extraction and Level Measurement Systems ..............................41 2008 CML Microsystems Plc 2 D/909B/2