Confidential Draft CS2300-OTP 3/27/08 Fractional-N Clock Multiplier with Internal LCO Features General Description The CS2300-OTP is an extremely versatile system Clock Multiplier / Jitter Reduction clocking device that utilizes a programmable phase lock Generates a Low Jitter 6 - 75 MHz Clock loop. The CS2300-OTP is based on a hybrid analog- from a Jittery or Intermittent 50 Hz to 30 digital PLL architecture comprised of a unique combina- MHz Clock Source tion of a Delta-Sigma Fractional-N Frequency Synthesizer and a Digital PLL. This architecture allows Internal LCO Reference Clock for generation of a low-jitter clock relative to an external Highly Accurate PLL Multiplication Factor noisy synchronization clock with frequencies as low as Maximum Error Less Than 1 PPM in High- 50 Hz. The CS2300-OTP has many configuration op- Resolution Mode tions which are set once prior to runtime. At runtime there are three hardware configuration pins available for One-Time Programmability mode and feature selection. Configurable Hardware Control Pins The CS2300-OTP is available in a 10-pin MSOP pack- Configurable Auxiliary Output age in Commercial (-10C to +70C) grade. Customer development kits are also available for custom device Minimal Board Space Required prototyping, small production programming, and device No External Analog Loop-filter evaluation. Please see Ordering Information on Components page 27 for complete details. 3.3 V Frequency Reference PLL Output Auxiliary Hardware Control Hardware Configuration Lock Indicator Output Fractional-N 6 to 75 MHz LCO Frequency Synthesizer PLL Output N 50 Hz to 30 MHz Frequency Reference Digital PLL & Fractional N Logic Output to Input Clock Ratio This document contains information for a new product. Advance Product Information Cirrus Logic reserves the right to modify this product without notice. Copyright Cirrus Logic, Inc. 2008 March 08 (All Rights Reserved) Confidential Draft 3/27/08 CS2300-OTP TABLE OF CONTENTS 1. PIN DESCRIPTION ................................................................................................................................. 4 2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 5 3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6 RECOMMENDED OPERATING CONDITIONS .................................................................................... 6 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6 DC ELECTRICAL CHARACTERISTICS ................................................................................................ 6 AC ELECTRICAL CHARACTERISTICS ................................................................................................ 7 4. ARCHITECTURE OVERVIEW ............................................................................................................... 8 4.1 Delta-Sigma Fractional-N Frequency Synthesizer ........................................................................... 8 4.2 Hybrid Analog-Digital Phase Locked Loop ...................................................................................... 8 5. APPLICATIONS ................................................................................................................................... 10 5.1 One Time Programmability ............................................................................................................ 10 5.2 Timing Reference Clock ................................................................................................................. 10 5.3 Frequency Reference Clock Input, CLK IN ................................................................................... 10 5.3.1 CLK IN Skipping Mode ......................................................................................................... 10 5.3.2 Adjusting the Minimum Loop Bandwidth for CLK IN ............................................................12 5.4 Output to Input Frequency Ratio Configuration ............................................................................. 13 5.4.1 User Defined Ratio (R ) ...................................................................................................... 13 UD 5.4.2 Manual Ratio Modifier (R-Mod) ............................................................................................. 14 5.4.3 Automatic Ratio Modifier (Auto R-Mod) ................................................................................ 14 5.4.4 Effective Ratio (R ) ............................................................................................................ 15 EFF 5.4.5 Ratio Configuration Summary ............................................................................................... 15 5.5 PLL Clock Output ........................................................................................................................... 16 5.6 Auxiliary Output .............................................................................................................................. 17 5.7 Mode Pin Functionality ................................................................................................................... 17 5.7.1 M1 and M0 Mode Pin Functionality ....................................................................................... 17 5.7.2 M2 Mode Pin Functionality .................................................................................................... 18 5.7.2.1 M2 Configured as Output Disable .............................................................................. 18 5.7.2.2 M2 Configured as R-Mod Enable .............................................................................. 18 5.7.2.3 M2 Configured as Auto R-Mod Enable ...................................................................... 18 5.7.2.4 M2 Configured as AuxOutSrc Override ..................................................................... 18 5.8 Clock Output Stability Considerations ............................................................................................ 19 5.8.1 Output Switching ................................................................................................................... 19 5.8.2 PLL Unlock Conditions .......................................................................................................... 19 6. PARAMETER DESCRIPTIONS ........................................................................................................... 20 6.1 Modal Configuration Sets ............................................................................................................... 20 6.1.1 R-Mod Selection (RModSel 1:0 ) ...........................................................................................20 6.1.2 Auxiliary Output Source Selection (AuxOutSrc 1:0 ) ............................................................. 21 6.1.3 Auto R-Modifier Enable (AutoRMod) ..................................................................................... 21 6.2 Ratio 0 - 3 ...................................................................................................................................... 21 6.3 Global Configuration Parameters ................................................................................................... 21 6.3.1 Clock Skip Enable (ClkSkipEn) ............................................................................................. 21 6.3.2 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 22 6.3.3 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 22 6.3.4 Low-Frequency Ratio Configuration (LFRatioCfg) ................................................................ 22 6.3.5 M2 Pin Configuration (M2Config 2:0 ) ................................................................................... 22 6.3.6 Clock Input Bandwidth (ClkIn BW 2:0 ) ................................................................................23 7. CALCULATING THE USER DEFINED RATIO .................................................................................... 24 7.1 High Resolution 12.20 Format ....................................................................................................... 24 7.2 High Multiplication 20.12 Format ................................................................................................... 24 8. PROGRAMMING INFORMATION ........................................................................................................ 25 9. PACKAGE DIMENSIONS .................................................................................................................... 26 DS844A1 2