CS2300CP-CZZ

CS2300-CP Fractional-N Clock Multiplier with Internal LCO Features General Description Clock Multiplier / Jitter Reduction The CS2300-CP is an extremely versatile system Generates a Low Jitter 6 - 75 MHz Clock clocking device that utilizes a programmable phase lock loop. The CS2300-CP is based on a hybrid ana- from a Jittery or Intermittent 50 Hz to 30 log-digital PLL architecture comprised of a unique MHz Clock Source combination of a Delta-Sigma Fractional-N Frequency Internal LC Oscillator for Timing Reference Synthesizer and a Digital PLL. This architecture allows Highly Accurate PLL Multiplication Factor for generation of a low-jitter clock relative to an exter- nal noisy synchronization clock at frequencies as low Maximum Error less than 1 PPM in High- as 50 Hz. The CS2300-CP supports both IC and SPI Resolution Mode for full software control. IC / SPI Control Port The CS2300-CP is available in a 10-pin MSOP pack- Configurable Auxiliary Output age in Commercial (-10C to +70C) and Automotive-D Minimal Board Space Required (-40C to +85C) and Automotive-E (-40C to +105C) No External Analog Loop-filter grades. Customer development kits are also available Components for device evaluation. Please see Ordering Informa- tion on page 31 for complete details. 3.3 V Frequency Reference IC/SPI IC / SPI PLL Output Software Control Auxiliary Output Lock Indicator Fractional-N 6 to 75 MHz LCO PLL Output Frequency Synthesizer N 50 Hz to 30 MHz Digital PLL & Fractional Frequency N Logic Reference Output to Input Clock Ratio Cirrus Logic Confidential OCT 15 Copyright Cirrus Logic, Inc. 20092015 CS2300-CP TABLE OF CONTENTS 1. PIN DESCRIPTION ................................................................................................................................. 5 2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 6 3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 7 RECOMMENDED OPERATING CONDITIONS .................................................................................... 7 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 7 DC ELECTRICAL CHARACTERISTICS ................................................................................................ 7 AC ELECTRICAL CHARACTERISTICS ................................................................................................ 8 PLL PERFORMANCE PLOTS ............................................................................................................... 9 CONTROL PORT SWITCHING CHARACTERISTICS- IC FORMAT ................................................. 10 CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT ............................................... 11 4. ARCHITECTURE OVERVIEW ............................................................................................................. 12 4.1 Delta-Sigma Fractional-N Frequency Synthesizer ......................................................................... 12 4.2 Hybrid Analog-Digital Phase Locked Loop ....................................................................................12 5. APPLICATIONS ................................................................................................................................... 14 5.1 Timing Reference Clock ................................................................................................................. 14 5.2 Frequency Reference Clock Input, CLK IN ................................................................................... 14 5.2.1 CLK IN Skipping Mode ......................................................................................................... 14 5.2.2 Adjusting the Minimum Loop Bandwidth for CLK IN ............................................................16 5.3 Output to Input Frequency Ratio Configuration ............................................................................. 17 5.3.1 User Defined Ratio (RUD) ..................................................................................................... 17 5.3.2 Ratio Modifier (R-Mod) .......................................................................................................... 18 5.3.3 Effective Ratio (REFF) .......................................................................................................... 18 5.3.4 Ratio Configuration Summary ............................................................................................... 19 5.4 PLL Clock Output ........................................................................................................................... 20 5.5 Auxiliary Output .............................................................................................................................. 20 5.6 Clock Output Stability Considerations ............................................................................................ 21 5.6.1 Output Switching ................................................................................................................... 21 5.6.2 PLL Unlock Conditions .......................................................................................................... 21 5.7 Required Power Up Sequencing .................................................................................................... 21 6. SPI / IC CONTROL PORT ................................................................................................................... 21 6.1 SPI Control ..................................................................................................................................... 22 6.2 IC Control ...................................................................................................................................... 22 6.3 Memory Address Pointer ............................................................................................................... 24 6.3.1 Map Auto Increment .............................................................................................................. 24 7. REGISTER QUICK REFERENCE ........................................................................................................ 24 8. REGISTER DESCRIPTIONS ................................................................................................................ 25 8.1 Device I.D. and Revision (Address 01h) ........................................................................................ 25 8.1.1 Device Identification (Device 4:0 ) - Read Only ..................................................................... 25 8.1.2 Device Revision (Revision 2:0 ) - Read Only ........................................................................ 25 8.2 Device Control (Address 02h) ........................................................................................................ 25 8.2.1 Unlock Indicator (Unlock) - Read Only .................................................................................. 25 8.2.2 Auxiliary Output Disable (AuxOutDis) ................................................................................... 25 8.2.3 PLL Clock Output Disable (ClkOutDis) .................................................................................. 26 8.3 Device Configuration 1 (Address 03h) ........................................................................................... 26 8.3.1 R-Mod Selection (RModSel 2:0 ) ...........................................................................................26 8.3.2 Auxiliary Output Source Selection (AuxOutSrc 1:0 ) ............................................................. 26 8.3.3 Enable Device Configuration Registers 1 (EnDevCfg1) ........................................................ 27 8.4 Global Configuration (Address 05h) ............................................................................................... 27 8.4.1 Device Configuration Freeze (Freeze) .................................................................................. 27 8.4.2 Enable Device Configuration Registers 2 (EnDevCfg2) ........................................................ 27 8.5 Ratio (Address 06h - 09h) .............................................................................................................. 27 8.6 Function Configuration 1 (Address 16h) ........................................................................................ 28 2 DS843F3