POGEE SEMICONDUCTOR AP54RHC504 Radiation Hardened 5-channel Level Translator with cold sparing and 3-state outputs 1.1 FEATURES 1 GENERAL DESCRIPTION 1.65VDCto5.5VDC operation The AP54RHC504 is a radiation-hardened by design 5- channel level translator with 3-state outputs that is Inputs tolerant up to 5.5 VDC at any V A or V Y CC CC ideally suited for space, medical imaging and other ap- plications demanding radiation tolerance and high re- Extended operating temperature range (-55C to liability. It is fabricated in a 180 nm CMOS process uti- +125C) lizing proprietary radiation-hardening techniques, de- Proprietary cold-sparing capability with zero livering high resiliency to single-event e ects (SEE) and static power penalty to a total ionizing dose (TID) up to 30 krad (Si). Built-in triple redundancy for enhanced reliabil- This device is a member of the Apogee Semiconductor ity AP54RHC logic family. All members of this family op- erate across a full 1.65 V to 5.5 V range providing the Internal power-on reset (POR) circuitry ensures system designer exibility in logic-level interfaces. The reliable power up and power down responses AP54RHC504 can operate across this range on both of during hot plug and cold sparing operations its supply voltage inputs, V A and V Y. CC CC Tri-state output drivers An output enable control pin allows the outputs to be placed in a high impedance (high-Z) state, simplify- Class 2 ESD protection (4000 V HBM, 500 V CDM) ing usage in applications with shared busses or mixed power domains. Additionally, the outputs are placed TID resilience of 30krad(Si) in high-Z when V A is not present, ensuring that no CC 2 loading or leakage paths are experienced at the output SEL resilient up to LET of 80MeV-cm /mg nodes when the input rail is not powered. 1.2 LOGIC DIAGRAM Zero-power penalty cold-sparing is supported, along with Class 2 ESD protection on all inputs and outputs. The AP54RHC504 logic function is shown below: A proprietary output stage and robust power-on reset (POR) circuit allow the AP54RHC504 to be cold-spared in any redundant conguration with no static power VCCA VCCY loss on any pad of the device. The redundant out- 1 14 8 put stage also features a high drive capability with low EN static power loss. 2 13 A1 Y1 The AP54RHC504 also features a triple-redundant de- 3 12 A2 Y2 sign throughout its entire circuitry, which allows it to be immune to single-event transients (SET) without re- 4 11 A3 Y3 quiring additional redundant devices. 5 10 A4 Y4 Ordering information may be found in Table 9 on Page 6 9 13. A5 Y5 7 GND Figure 1: AP54RHC504 logic diagram COPYRIGHT 2022 APOGEE SEMICONDUCTOR REVISED: 2022-05-08 DOC ID: 601-000-025-A08 (SUBMIT DOCUMENTATION FEEDBACK) 1 / 14AP54RHC504 Rad-Hard 5-channel Level Translator POGEE SEMICONDUCTOR DATASHEET with cold sparing and 3-state outputs CONTENTS 1 General Description 1 5.6 Characteristics Measurement Information 8 1.1 Features 1 6 Detailed Description 9 1.2 Logic Diagram . 1 7 Applications Information 10 2 Acronyms and Abbreviations 2 7.1 Applications Example 10 3 Logic Data 3 7.2 Power Supply Recommendations . 11 7.3 Application Tips . 11 4 Pin Conguration 3 8 Packaging Information 12 5 Electrical Characteristics 4 5.1 Absolute Maximum Ratings . 4 9 Ordering Information 13 5.2 Recommended Operating Conditions . 5 5.3 Static Characteristics 6 10 Revision History 13 5.4 Dynamic Characteristics . 7 5.5 Radiation Resilience . 7 11 Legal 14 LIST OF TABLES 1 Truth Table 3 6 DC Electrical Characteristics 6 2 Device Pinout . 3 7 AC Electrical Characteristics 7 3 Absolute Maximum Ratings . 4 8 Radiation Resilience Characteristics . 7 4 Recommended Operating Conditions . 5 9 Ordering Information 13 5 Thermal Information . 5 LIST OF FIGURES 1 AP54RHC504 logic diagram . 1 6 Input Pin Structure 9 2 Device Pinout . 3 7 Output Pin Structure . 9 3 Load Circuit 8 8 Cold Spare Example . 10 4 Propagation Delay 8 9 Package Mechanical Drawing 12 5 Enable and Disable Timing . 8 10 Part Number Decoder 13 2 ACRONYMS AND ABBREVIATIONS ESD Electrostatic Discharge POR Power On Reset RHA Radiation Hardness Assurance SEE Single Event E ects SEL Single Event Latchup SET Single Event Transient TID Total Ionizing Dose TMR Triple Modular Redundancy CDM Charged-device Model HBM Human-body Model COPYRIGHT 2022 APOGEE SEMICONDUCTOR REVISED: 2022-05-08 DOC ID: 601-000-025-A08 (SUBMIT DOCUMENTATION FEEDBACK) 2 / 14