MAX9485 19-3315 Rev 0 7/04 Programmable Audio Clock Generator General Description Features The MAX9485 programmable multiple-output clock 27MHz Crystal with 30ppm Frequency Reference generator provides a cost-efficient solution for MPEG-2 Two Buffered Output Ports with Multiple Audio audio systems such as DVD players, DVD drives for Clocks: 256, 384, or 768 Times f S multimedia PCs, digital HDTV systems, home entertain- ment centers, and set-top boxes. Supports Standard and Double Sampling Rates (12kHz, 32kHz, 44.1kHz, 48kHz, 64kHz, 88.2 kHz, The MAX9485 accepts an input reference frequency of 27MHz from a crystal or system reference clock. The and 96kHz) device provides two buffered clock outputs of 256, 384, 2 I C Interface or Hardwired Output Clock Selection or 768 times the chosen sampling frequency (f ) select- S 2 Separate Output Clock Enable ed through an I C interface or hardwired inputs. Sampling frequencies of 12kHz, 32kHz, 44.1kHz, Low Jitter Typical 21ps (RMS at 73.728MHz) 48kHz, 64kHz, 88.2kHz, or 96kHz are available. The No External Components for PLL MAX9485 also offers a buffered 27MHz output and an integrated voltage-controlled oscillator (VCXO) that is Integrated VCXO with 200ppm Tuning Range tuned by a DC voltage generated from the MPEG Small Footprint, Thin QFN Package, 4mm x 4mm processor. The use of VCXO allows the audio system clock to lock with the overall system clock. The MAX9485 features the lowest jitter in its class, guar- Ordering Information anteeing excellent dynamic performance with audio ADCs and DACs in an MPEG-2 audio system. The PART TEMP RANGE PIN-PACKAGE device operates with a 3.3V supply and is specified over the -40C to +85C extended temperature range. The MAX9485ETP -40C to +85C 20 Thin QFN-EP* MAX9485 is offered in 6.5mm x 4.4mm 20-pin TSSOP MAX9485EUP -40C to +85C 20 TSSOP and 4mm x 4mm 20-pin thin QFN packages. *EP = Exposed pad. Applications Digital TVs DVD Players Set-Top Boxes HDTVs Home Entertainment Centers Pin Configurations TOP VIEW V 1 20 SAO2 DD P GND P 2 19 SAO1 TUN 3 18 MCLK TUN 1 15 V DD X1 4 17 V DD X1 2 14 CLK OUT2 MAX9485 X2 5 16 CLK OUT2 MAX9485 X2 3 13 GND EXPOSED PAD V 6 15 GND DD V 4 12 CLK OUT1 DD (GROUND) SCL/FS0 7 14 CLK OUT1 SCL/FS0 5 11 MODE SDA/FS1 8 13 MODE FS2 9 12 RST GND 10 11 GND THIN QFN TSSOP Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim s website at www.maxim-ic.com. EVALUATION KIT AVAILABLE SDA/FS1 6 20 GND P FS2 7 19 V DD P GND 8 18 SAO2 GND 9 17 SAO1 RST 10 16 MCLKProgrammable Audio Clock Generator ABSOLUTE MAXIMUM RATINGS V V to GND ...............................................-0.3V to +4.0V Storage Temperature Range .............................-65C to +150C DD, DD P GND P to GND...................................................................0.3V Maximum Junction Temperature .....................................+150C All Inputs and Outputs to GND...................-0.3V to (V + 0.3V) ESD Protection DD Short-Circuit Duration of Outputs to GND..................Continuous Human Body Model (R = 1.5k, C = 100pF)...........> 2kV D S Continuous Power Dissipation (T = +70C) Lead Temperature (soldering, 10s) .................................+300C A 20-Pin TSSOP (derate 11mW/C above +70C) ......... 879mW 20-Lead Thin QFN (derate 16.9mW/C above +70C).............................................................1349mW Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (V = V = 3.0V to 3.6V, T = -40C to +85C, unless otherwise noted. Typical values are at T = +25C, V = V = 3.3V.) DD DD P A A DD DD P (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LVCMOS/LVTTL INPUTS (MODE, RST, X1) (Note 2) High Level-Input Voltage V 2.0 V V IH1 DD Low Level-Input Voltage V 0.0 0.8 V IL1 Input Current I Input voltage = 0 or V -20 +20 A IL1 DD THREE-LEVEL INPUTS (FS0, FS1, FS2, SAO1, SAO2) High Level-Input Voltage V 2.5 V V IH2 DD Low Level-Input Voltage V 0.0 0.8 V IL2 Input Open Level V Input open 1.3 2.0 V IO2 Input Current I Input voltage = 0 or V -10 +10 A IN DD LVCMOS/LVTTL OUTPUTS (CLK OUT1, CLK OUT2, MCLK) Output High Level V I = -4mA V - 0.6 V OH1 OH1 DD Output Low Level V I = 4mA 0.4 V OL1 OL1 2 I C INTERFACE INPUT AND OUTPUT (SCL, SDA) Input High Level V 0.7 x V V V IH3 DD DD Input Low Level V 0 0.3 x V V IL3 DD Input Current I Input voltage = 0 or V -1 +1 A IN DD Low-Level Output V I = 4mA 0.4 V OL3 OL3 Input Capacitance C 8.4 pF IN POWER SUPPLY (V , V ) DD DD P V DD, Power-Supply Ranges 3.0 3.3 3.6 V V DD P CLK OUT1, CLK OUT2 at 73.728MHz, Power-Supply Current I +I 12 mA DD DD P no load, V = 3.0V TUN 2 MAX9485