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MAX5487PMB1#

MAX5487PMB1# electronic component of Analog Devices

Datasheet
Digital Potentiometer Development Tools MAX5487 Peripheral Module

Manufacturer: Analog Devices
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1: AUD 61.5478 ( AUD 67.7 Inc GST) ea
Line Total: AUD 61.5478 ( AUD 67.7 Inc GST)

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MAX5487PMB1#
Analog Devices

1 : AUD 61.5478

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Ships to you between Fri. 12 Jul to Thu. 18 Jul

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MAX5487PMB1#
Analog Devices

2 : AUD 36.1801

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MAX5487PMB1#
Analog Devices

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10 : AUD 66.381
25 : AUD 61.849
100 : AUD 58.901

     
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19-6326 Rev 0 5/12 MAX5487PMB1 Peripheral Module General Description Features The MAX5487PMB1 peripheral module provides the nec- S Dual, 256-Tap, Linear-Taper 10kI Digital essary hardware to interface the MAX5487 dual linear- Potentiometers taper digital potentiometer to any system that utilizes S Wiper Position Stored in Nonvolatile Memory PmodK-compatible expansion ports configurable for SPI (EEPROM) and Recalled on Power-Up or by an communication. These digital potentiometers function Interface Command - like mechanical potentiometers with a simple 3-wire SPI S IC is Pin-Compatible with 50kI (MAX5488) and compatible interface that programs the wipers to any one 100kI Versions (MAX5489) of 256 tap positions. The terminals of each potentiometer S Solder Links Allowing Configuration as Variable are available at the output connector for attachment to Resistors external circuitry. Refer to the MAX5487/MAX5488/MAX5489 IC data sheet S 6-Pin Pmod-Compatible Connector (SPI) for detailed information regarding operation of the IC. S Example Software Written in C for Portability S RoHS Compliant S Proven PCB Layout S Fully Assembled and Tested Ordering Information appears at end of data sheet. MAX5487PMB1 Peripheral Module Pmod is a trademark of Digilent Inc. Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxims website at www.maxim-ic.com.MAX5487PMB1 Peripheral Module Component List DESIGNATION QTY DESCRIPTION DESIGNATION QTY DESCRIPTION R1, R2, R3 3 150I Q5% resistors (0603) 0.1FF Q10%, 16V X7R ceramic C1 1 capacitor (0603) Dual, nonvolatile, 10kI digital Murata GRM188R71C104KA01D U1 1 potentiometer (16 TQFN-EP*) Maxim MAX5487ETE+ J1 1 6-pin right-angle male header J2 1 6-pin straight male header 1 PCB: EPCB5487PM1 *EP = Exposed pad. Component Supplier SUPPLIER PHONE WEBSITE Murata Electronics North America, Inc. 770-436-1300 www.murata-northamerica.com Note: Indicate that you are using the MAX5487PMB1 when contacting this component supplier. Table 1. Connector J1 (SPI Communication) Detailed Description PIN SIGNAL DESCRIPTION SPI Interface Chip enable. Must be asserted low to The MAX5487PMB1 peripheral module can plug directly 1 SS enable the SPI interface. into a Pmod-compatible port (configured for SPI) through 2 MOSI MAX5487 serial-data input connector J1. For information on the SPI protocol, refer to the MAX5487/MAX5488/MAX5489 IC data sheet. 3 N.C. Not connected 4 SCK MAX5487 serial-clock input J1 provides connection of the module to the Pmod 5 GND Ground host. The pin functions and pin assignments adhere to the Pmod standard recommended by Digilent Inc. See 6 VCC Power supply Table 1. Table 2. Connector J2 (SPI Communication) Connector J2 provides connection to the potentiometers. See Table 2. PIN SIGNAL DESCRIPTION 1 HA High terminal of resistor A Software and FPGA Code 2 WA Wiper terminal of resistor A Example software and drivers are available that execute directly without modification on several FPGA devel- 3 LA Low terminal of resistor A opment boards that support an integrated or synthe- 4 HB High terminal of resistor B sized microprocessor. These boards include the Digilent 5 WB Wiper terminal of resistor B Nexys 3, Avnet LX9, and Avnet ZEDBoard, although 6 LB Low terminal of resistor B other platforms can be added over time. Maxim provides complete Xilinx ISE projects containing HDL, Platform The source code is written in standard ANSI C format, and Studio, and SDK projects. In addition, a synthesized bit all API documentation including theory/operation, register stream, ready for FPGA download, is provided for the description, and function prototypes are documented in demonstration application. the API interface file (maximDeviceSpecificUtilities.h & .c). The software project (for the SDK) contains several The complete software kit is available for download at source files intended to accelerate customer evalu- www.maxim-ic.com. Quick start instructions are also ation and design. These include a base application available as a separate document. (maximModules.c) that demonstrates module function- ality and uses an API interface (maximDeviceSpecific Utilities.c) to set and access Maxim device functions within a specific module. Maxim Integrated Products 2

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