EVAL-ADICUP360

ADuCM360/ADuCM361 Hardware User Guide UG-367 One Technology Way P.O. Box 9106 Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 www.analog.com Using the ADuCM360/ADuCM361 Low Power, Precision Analog Microcontroller with Dual Sigma-Delta ADCs, ARM Cortex-M3 SCOPE This user guide provides a detailed description of the ADuCM360/ADuCM361 functionality and features. DISCLAIMER Information furnished by Analog Devices, Inc., is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. ON-CHIP ON-CHIP 12-BIT POWER-ON DAC BUFFER RESET 1.8V ANALOG 1.8V DIGITAL DAC RESET LDO LDO AVDD V BIAS AGND GENERATOR ON-CHIP XTALO OSCILLATOR (1% TYPICAL) XTALI 16MHz V 24-BIT REF ARM AIN0 - ADC CORTEX-M3 PROCESSOR AIN1 GPIO PORTS AIN2 - MOD2 SINC3/4 AMP BUF 16MHz UART PORTS GAIN MODULATOR FILTER AIN3 2 SPI PORTS 2 I C PORTS AIN4/IEXC AIN5/IEXC TIMER0 19 GENERAL- AIN6/IEXC SINC2 MEMORY TIMER1 PURPOSE FILTER 128kB FLASH WATCHDOG I/O PORTS AIN7/VBIAS0/IEXC/ MUX 8kB SRAM WAKE-UP TIMER EXTREF2IN+ PWM AIN8/EXTREF2IN V 24-BIT REF AIN9/DACBUFF+ - ADC SERIAL WIRE DMA AND DEBUG, AIN10 INTERRUPT PROGRAMMING AIN11/VBIAS1 - MOD2 SINC3/4 CONTROLLER AND DEBUG AMP BUF GAIN MODULATOR FILTER SELECTABLE SWDIO V DAC, TEMP, REF IOVDD/4, SOURCES SWCLK AVDD/4 PRECISION REFERENCE ADuCM360 DVDD REG IREF BUFFER CURRENT AVDD REG SOURCES BUFFER GND SW VREF VREF+ INT REF IOVDD IOVDD Figure 1. ADuCM360 Block Diagram PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. D Page 1 of 176 10464-001ADuCM360/ADuCM361 Hardware User Guide UG-367 TABLE OF CONTENTS Scope .................................................................................................. 1 System Exceptions and Peripheral Interrupts............................. 56 Disclaimer .......................................................................................... 1 Cortex-M3 and Fault Management ......................................... 56 Revision History ............................................................................... 4 External Interrupt Configuration ............................................ 59 Using the ADuCM360/ADuCM361 Hardware User Guide ....... 5 Interrupt Memory Mapped Registers ...................................... 59 Number Notations ........................................................................ 5 DMA Controller ............................................................................. 64 Register Access Conventions ...................................................... 5 DMA Features ............................................................................. 64 Acronyms and Abbreviations ..................................................... 5 DMA Overview .......................................................................... 64 Introduction to the ADuCM360/ADuCM361 ............................. 6 DMA Operation ......................................................................... 64 Main Features of ADuCM360/ADuCM361 ............................. 7 Error Management ..................................................................... 64 Memory Organization ................................................................. 9 Interrupts ..................................................................................... 64 Clocking Architecture .................................................................... 10 DMA Priority .............................................................................. 65 Clocking Architecture Features ................................................ 10 Channel Control Data Structure .............................................. 65 Clocking Architecture Block Diagram .................................... 10 Control Data Configuration ..................................................... 66 Clocking Architecture Overview.............................................. 11 DMA Transfer Types (CHNL CFG 2:0 ) ............................... 67 Clocking Architecture Operation............................................. 11 Address Calculation ................................................................... 69 Clocking Architecture Memory Mapped Registers ............... 11 DMA Memory Mapped Registers ............................................ 72 Power Management Unit ............................................................... 15 Flash Controller .............................................................................. 86 Power Management Unit Features ........................................... 15 Flash Controller Features .......................................................... 86 Power Management Unit Overview ......................................... 15 Flash Controller Overview ........................................................ 86 Power Management Unit Operation ........................................ 15 Flash Memory Organization ..................................................... 86 Power Management Unit Memory Mapped Registers .......... 16 Writing to Flash/EE Memory ................................................... 87 Cortex-M3 Processor ..................................................................... 18 Erasing Flash/EE Memory ........................................................ 87 Cortex-M3 Processor Features ................................................. 18 Flash Controller Performance and Command Duration ..... 88 Cortex-M3 Processor Overview ............................................... 18 Flash Protection .......................................................................... 88 Cortex-M3 Processor Operation .............................................. 18 Flash Controller Failure Analysis Key ..................................... 89 Related Documents .................................................................... 19 Flash Integrity Signature Feature ............................................. 89 ADC Circuit .................................................................................... 20 Integrity of the Kernel ................................................................ 89 ADC Circuit Features ................................................................ 20 Abort Using Interrupts .............................................................. 89 ADC Circuit Block Diagram..................................................... 20 Flash Controller Memory Mapped Registers ......................... 90 ADC Circuit Overview .............................................................. 20 Reset ................................................................................................. 99 ADC Circuit Operation ............................................................. 21 Reset Features ............................................................................. 99 Other ADC Support Circuits .................................................... 25 Reset Operation .......................................................................... 99 Other ADC Details ..................................................................... 28 Reset Memory Mapped Registers .......................................... 100 ADC Circuit Memory Mapped Registers ............................... 35 Digital I/Os .................................................................................... 101 DAC .................................................................................................. 51 Digital I/Os Features ................................................................ 101 DAC Features .............................................................................. 51 Digital I/Os Block Diagram .................................................... 101 DAC Overview ............................................................................ 51 Digital I/Os Overview.............................................................. 101 DAC Operation ........................................................................... 51 Digital I/Os Operation............................................................. 101 DAC DMA Operation................................................................ 53 Digital Port Multiplex .............................................................. 103 DAC Memory Mapped Registers ............................................. 54 GPIO Memory Mapped Registers .......................................... 104 Rev. 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