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ADV7341BSTZ

ADV7341BSTZ electronic component of Analog Devices

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Analog Devices Video ICs 6 DAC 12-bit 4xOS HDTV Video Encoder

Manufacturer: Analog Devices
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1: AUD 38.1674 ( AUD 41.98 Inc GST) ea
Line Total: AUD 38.1674 ( AUD 41.98 Inc GST)

21 - Global Stock
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Mon. 29 Jul to Thu. 01 Aug
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Ships to you between
Mon. 29 Jul to Thu. 01 Aug

MOQ : 1
Multiples : 1

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ADV7341BSTZ
Analog Devices

1 : AUD 38.1674
5 : AUD 34.835
30 : AUD 33.3199

     
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Multiformat Video Encoder, Six 12-Bit Noise Shaped Video DACS Data Sheet ADV7340/ADV7341 FEATURES Undershoot limiter Dual data rate (DDR) input support 74.25 MHz 20-/30-bit high definition input support Enhanced definition (ED) programmable features Compliant with SMPTE 274 M (1080i), 296 M (720p), (525p/625p) and 240 M (1035i) 8 oversampling (216 MHz output) 6 Noise Shaped Video (NSV) 12-bit video DACs Internal test pattern generator 16 (216 MHz) DAC oversampling for SD Black bar, hatch, flat field/frame 8 (216 MHz) DAC oversampling for ED Individual Y and PrPb output delay 4 (297 MHz) DAC oversampling for HD Gamma correction 37 mA maximum DAC output current Programmable adaptive filter control NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support Fully programmable YCrCb to RGB matrix NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz) Undershoot limiter Multiformat video input support Macrovision Rev 1.2 (525p/625p) (ADV7340 only) 4:2:2 YCrCb (SD, ED, and HD) CGMS (525p/625p) and CGMS Type B (525p) 4:4:4 YCrCb (ED and HD) Dual data rate (DDR) input support 4:4:4 RGB (SD, ED, and HD) Standard definition (SD) programmable features Multiformat video output support 16 oversampling (216 MHz) Composite (CVBS) and S-Video (Y-C) Internal test pattern generator Component YPrPb (SD, ED, and HD) Color and black bar Component RGB (SD, ED, and HD) Controlled edge rates for start and end of active video Macrovision Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant Individual Y and PrPb output delay Simultaneous SD and ED/HD operation Undershoot limiter EIA/CEA-861B compliance support Gamma correction Copy generation management system (CGMS) Digital noise reduction (DNR) Closed captioning and wide screen signaling (WSS) Multiple chroma and luma filters Integrated subcarrier locking to external video source Luma-SSAF filter with programmable gain/attenuation Complete on-chip video timing generator PrPb SSAF On-chip test pattern generation Separate pedestal control on component and On-board voltage reference (optional external input) composite/S-Video output Programmable features VCR FF/RW sync mode Luma and chroma filter responses Macrovision Rev 7.1.L1 (ADV7340 only) Vertical blanking interval (VBI) Copy generation management system (CGMS) Subcarrier frequency (F ) and phase SC Wide screen signaling (WSS) Luma delay Closed captioning High definition (HD) programmable features 2 Serial MPU interface with I C compatibility (720p/1080i/1035i) 3.3 V analog operation 4 oversampling (297 MHz) 1.8 V digital operation Internal test pattern generator 1.8 V or 3.3 V I/O operation Fully programmable YCrCb to RGB matrix Temperature range: 40C to +85C Gamma correction Programmable adaptive filter control APPLICATIONS Programmable sharpness filter control DVD recorders and players CGMS (720p/1080i) and CGMS Type B (720p/1080i) High definition Blu-ray DVD players Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 2006-2012 Analog Devices, Inc. All rights reserved. ADV7340/ADV7341 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 SD Subcarrier Frequency Lock ................................................. 55 Applications ....................................................................................... 1 SD VCR FF/RW Sync ................................................................ 55 Revision History ............................................................................... 4 Vertical Blanking Interval ......................................................... 55 General Description ......................................................................... 5 SD Subcarrier Frequency Control ............................................ 56 Functional Block Diagram .............................................................. 6 SD Noninterlaced Mode ............................................................ 56 Specifications ..................................................................................... 7 SD Square Pixel Mode ............................................................... 56 Power Supply and Voltage Specifications .................................. 7 Filters............................................................................................ 57 Voltage Reference Specifications ................................................ 7 ED/HD Test Pattern Color Controls ....................................... 58 Input Clock Specifications .......................................................... 7 Color Space Conversion Matrix ............................................... 59 Analog Output Specifications ..................................................... 8 SD Luma and Color Scale Control ........................................... 60 Digital Input/Output Specifications3.3 V ............................. 8 SD Hue Adjust Control .............................................................. 60 Digital Input/Output Specifications1.8 V ............................. 8 SD Brightness Detect ................................................................. 61 Digital Timing Specifications3.3 V ........................................ 9 SD Brightness Control ............................................................... 61 Digital Timing Specifications1.8 V ...................................... 10 SD Input Standard Autodetection ............................................ 61 MPU Port Timing Specifications ............................................. 11 Double Buffering ........................................................................ 62 Power Specifications .................................................................. 11 Programmable DAC Gain Control .......................................... 62 Video Performance Specifications ........................................... 12 Gamma Correction .................................................................... 62 Timing Diagrams ............................................................................ 13 ED/HD Sharpness Filter and Adaptive Filter Controls ........ 64 Absolute Maximum Ratings .......................................................... 21 ED/HD Sharpness Filter and Adaptive Filter Application Examples ...................................................................................... 65 Thermal Resistance .................................................................... 21 SD Digital Noise Reduction ...................................................... 66 ESD Caution ................................................................................ 21 SD Active Video Edge Control ................................................. 67 Pin Configuration and Function Descriptions ........................... 22 External Horizontal and Vertical Synchronization Control . 69 Typical Performance Characteristics ........................................... 24 Low Power Mode ........................................................................ 70 MPU Port Description ................................................................... 29 2 Cable Detection .......................................................................... 70 I C Operation .............................................................................. 29 DAC Autopower-Down ............................................................. 70 Register Map Access ....................................................................... 31 Sleep Mode .................................................................................. 71 Register Programming ............................................................... 31 Pixel and Control Port Readback ............................................. 71 Subaddress Register (SR7 to SR0) ............................................ 31 Reset Mechanism........................................................................ 71 Input Configuration ....................................................................... 49 SD Teletext Insertion ................................................................. 71 Standard Definition Only .......................................................... 49 Printed Circuit Board Layout and Design .................................. 73 Enhanced Definition/High Definition Only .......................... 51 Unused Pins ................................................................................ 73 Simultaneous Standard Definition and Enhanced Definition/High Definition ....................................................... 51 DAC Configurations .................................................................. 73 Enhanced Definition Only (at 54 MHz) ................................. 52 Voltage Reference ....................................................................... 73 Output Configuration .................................................................... 53 Video Output Buffer and Optional Output Filter .................. 73 Design Features ............................................................................... 54 Printed Circuit Board (PCB) Layout ....................................... 74 Output Oversampling ................................................................ 54 Typical Application Circuit ....................................................... 76 Copy Generation Management System ....................................... 77 HD Interlace External P HSYNC and P VSYNC Considerations ............................................................................ 54 SD CGMS .................................................................................... 77 ED/HD Timing Reset ................................................................ 55 ED CGMS .................................................................................... 77 Rev. C Page 2 of 108

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