High Speed, 3.3 V/5 V Quad 2:1 Mux/Demux (4-Bit, 1 of 2) Bus Switch ADG3257 FUNCTIONAL BLOCK DIAGRAM FEATURES 1B 1 1A 100 ps propagation delay through the switch 1B 2 2 switches connect inputs to outputs 2B 1 2A Data rates up to 933 Mbps 2B 2 Single 3.3 V/5 V supply operation 3B 1 3A Level translation operation 3B 2 Ultralow quiescent supply current (1 nA typical) 4B 1 4A 3.5 ns switching 4B 2 Switches remain in the off state when power is off Standard 3257 type pinout APPLICATIONS LOGIC Bus switching Bus isolation S BE Level translation Figure 1. Memory switching/interleaving GENERAL DESCRIPTION The ADG3257 is a CMOS bus switch comprised of four 2:1 PRODUCT HIGHLIGHTS multiplexers/demultiplexers with high impedance outputs. The 1. 0.1 ns propagation delay through switch. device is manufactured on a CMOS process. This provides low 2. 2 switches connect inputs to outputs. power dissipation yet high switching speed and very low on resistance, allowing the inputs to be connected to the outputs 3. Bidirectional operation. without adding propagation delay or generating additional 4. Ultralow power dissipation. ground bounce noise. 5. 16-lead QSOP package. The ADG3257 operates from a single 3.3 V/5 V supply. The control logic for each switch is shown in Table 1. These switches are bidirectional when on. In the off state, signal levels are blocked up to the supplies. When the power supply is off, the switches remain in the off state, isolating Port A and Port B. This bus switch is suited to both switching and level translation applications. It can be used in applications requiring level trans- lation from 3.3 V to 2.5 V when powered from 3.3 V. Additionally, with a diode connected in series with 5 V VDD, the ADG3257 may also be used in applications requiring 5 V to 3.3 V level translation. Table 1. Truth Table BE S Function H X Disable L L A = B1 L H A = B2 Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no re- sponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20022008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 02914-001ADG3257 TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions ..............................6 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................7 Functional Block Diagram .............................................................. 1 Test Circuits ........................................................................................9 General Description ......................................................................... 1 Applications Information .............................................................. 10 Product Highlights ........................................................................... 1 Mixed Voltage Operation, Level Translation .......................... 10 Revision History ............................................................................... 2 Memory Switching ..................................................................... 10 Specif icat ions ..................................................................................... 3 Outline Dimensions ....................................................................... 11 Absolute Maximum Ratings ............................................................ 5 Ordering Guide .......................................................................... 11 ESD Caution .................................................................................. 5 REVISION HISTORY 03/08Rev. D to Rev. E Updated Format .................................................................... Universal Changes to Features .............................................................................1 Changes to General Description .......................................................1 Changes to Absolute Maximum Ratings ..........................................5 Changes to Pin Configuration and Function Descriptions ...........6 Changes to Test Circuits .....................................................................9 Changes to Ordering Guide ...............................................................11 11/04Rev. C to Rev. D Changes to Specifications ...................................................................2 Changes to Ordering Guide ...............................................................4 04/03Rev. A to Rev. B Updated Outline Dimensions ............................................................8 06/02Rev. 0 to Rev. A Edits to Features ...................................................................................1 Rev. E Page 2 of 12