Two Selectable Inputs, 10 LVPECL Outputs, SiGe Clock Fanout Buffer Data Sheet ADCLK950 FEATURES FUNCTIONAL BLOCK DIAGRAM 2 selectable differential inputs LVPECL ADCLK950 4.8 GHz operating frequency Q0 75 fs rms broadband random jitter Q0 On-chip input terminations Q1 3.3 V power supply Q1 Q2 APPLICATIONS Q2 Low jitter clock distribution Clock and data signal restoration Q3 V 0 REFERENCE Level translation REF Q3 Wireless communications Wired communications Q4 V 0 T Medical and industrial imaging Q4 CLK0 ATE and high performance instrumentation Q5 CLK0 V 1 Q5 T GENERAL DESCRIPTION CLK1 Q6 The ADCLK950 is an ultrafast clock fanout buffer fabricated Q6 CLK1 on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process. This device is designed for high speed Q7 applications requiring low jitter. IN SEL Q7 The device has two selectable differential inputs via the IN SEL Q8 V 1 control pin. Both inputs are equipped with center tapped, REFERENCE REF differential, 100 on-chip termination resistors. The inputs Q8 accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended), Q9 and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A Q9 VREFx pin is available for biasing ac-coupled inputs. The ADCLK950 features 10 full-swing emitter coupled logic Figure 1. (ECL) output drivers. For LVPECL (positive ECL) operation, bias V to the positive supply and V to ground. For ECL CC EE operation, bias V to ground and V to the negative supply. CC EE The output stages are designed to directly drive 800 mV each side into 50 terminated to VCC 2 V for a total differential output swing of 1.6 V. The ADCLK950 is available in a 40-lead LFCSP and specified for operation over the standard industrial temperature range of 40C to +85C. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20092016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 08279-001ADCLK950 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions ..............................6 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................7 General Description ......................................................................... 1 Functional Description .....................................................................9 Functional Block Diagram .............................................................. 1 Clock Inputs ...................................................................................9 Revision History ............................................................................... 2 Clock Outputs ................................................................................9 Specifications ..................................................................................... 3 Clock Input Select (IN SEL) Settings...................................... 10 Electrical Characteristics ............................................................. 3 PCB Layout Considerations ...................................................... 10 Absolute Maximum Ratings ............................................................ 5 Input Termination Options ....................................................... 11 Determining Junction Temperature .......................................... 5 Outline Dimensions ....................................................................... 12 ESD Caution .................................................................................. 5 Ordering Guide .......................................................................... 12 Thermal Performance .................................................................. 5 REVISION HISTORY 8/2016Rev. A to Rev. B Changed CP-40-8 to CP-40-16 .................................... Throughout Changes to Figure 2 and Table 7 ..................................................... 6 Updated Outline Dimensions ....................................................... 12 Changes to Ordering Guide .......................................................... 12 6/2010Rev. 0 to Rev. A Changed Output Voltage Differential Parameter to Output Voltage, Single Ended Parameter, Table 1 ..................................... 3 Changes to Output Voltage, Single Ended Parameter, Table 1 ... 3 7/2009Revision 0: Initial Version Rev. B Page 2 of 12