Complete 10-Bit 18 MSPS a CCD Signal Processor AD9806 FEATURES PRODUCT DESCRIPTION The AD9806 is a complete analog signal processor for CCD Pin-Compatible with Industry Standard AD9803 applications. It features an 18 MHz single-channel architecture 18 MSPS Correlated Double Sampler (CDS) designed to sample and condition the outputs of interlaced and Low Noise PGA with 0 dB to 34 dB Gain Range progressive scan area CCD arrays. The AD9806s signal chain Low Noise Clamp Circuits consists of an input clamp, correlated double sampler (CDS), Analog Preblanking Function digitally programmable gain amplifier (PGA), black level clamp, 10-Bit 18 MSPS A/D Converter and 10-bit A/D converter. Additional input modes are provided AUX Input with Input Clamp and PGA for processing analog video signals. Direct ADC Input with Input Clamp The internal registers are programmed through a 3-wire serial AUXMID Input with PGA digital interface. Programmable features include gain adjust- 3-Wire Serial Interface for Digital Control ment, black level adjustment, input configuration, and power- Two Auxiliary 8-Bit DACs down modes. 3 V Single Supply Operation Low Power: 65 mW 2.7 V Supply The AD9806 operates from a single 3 V power supply, typically 48-Lead LQFP Package dissipating 75 mW. Packaged in a space-saving 48-lead LQFP, the AD9806 is specified over an operating temperature range of APPLICATIONS 20C to +85 C. Camcorders (8 mm and DVC) Digital Still Cameras FUNCTIONAL BLOCK DIAGRAM PBLK CLPOB CLAMP 0dB~34dB AD9806 PGA CCDIN CDS 10 ADC MUX S/H DOUT CLAMP CLPDM 0dB~15dB 4~14dB VRT PGA PGA REF VRB 8-BIT 10-BIT DAC1 DAC DAC CLAMP 8-BIT INTF DAC2 DAC TIMING GENERATOR 3 3-W INTF ADCIN AUXIN AUXMID SHP SHD ADCCLK REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: AD9806SPECIFICATIONS GENERAL SPECIFICATIONS (T to T , AVDD = DVDD = 3.0 V, f = 18 MHz, unless otherwise noted.) MIN MAX ADCCLK Parameter Min Typ Max Unit TEMPERATURE RANGE Operating 20 +85 C Storage 65 +150 C POWER SUPPLY VOLTAGE (For Functional Operation) 2.7 3.6 V Analog, Digital, Digital Driver POWER CONSUMPTION (Selected through Serial Interface D-Reg) Normal Operation (D-Reg 00) (Specified Under Each Mode of Operation) High-Speed AUX Mode (D-Reg 01) (Specified Under AUX-Mode) Reference Standby (D-Reg 10) 5 mW Total Shut-Down Mode (D-Reg 11) 1 mW MAXIMUM CLOCK RATE (Specified Under Each Mode of Operation) MHz A/D CONVERTER Resolution 10 Bits Differential Nonlinearity (DNL) 0.5 1.0 LSB No Missing Codes GUARANTEED Full-Scale Input Voltage 1.0 V VOLTAGE REFERENCE Reference Top Voltage (VRT) 2.0 V Reference Bottom Voltage (VRB) 1.0 V Specifications subject to change without notice. DIGITAL SPECIFICATIONS (DRVDD = 2.7 V, C = 20 pF.) L Parameter Symbol Min Typ Max Unit LOGIC INPUTS High Level Input Voltage V 2.1 V IH Low Level Input Voltage V 0.6 V IL High Level Input Current I 10 A IH Low Level Input Current I 10 A IL Input Capacitance C 10 pF IN LOGIC OUTPUTS High Level Output Voltage (I = 2 mA) V 2.2 V OH OH Low Level Output Voltage (I = 2 mA) V 0.5 V OL OL SERIAL INTERFACE TIMING (Figure 7) Maximum SCLK Frequency 10 MHz SDATA to SCLK Setup t 10 ns DS SCLK to SDATA Hold t 10 ns DH SLOAD to SCLK Setup t 10 ns LS SCLK to SLOAD Hold t 10 ns LH Specifications subject to change without notice. 2 REV. 0