1.2 GHz Clock Distribution IC, 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs AD9512 FEATURES FUNCTIONAL BLOCK DIAGRAM VS GND Two 1.6 GHz, differential clock inputs RSET 5 programmable dividers, 1 to 32, all integers VREF SYNCB, SYNC SYNC Phase select for output-to-output coarse delay adjust FUNCTION RESETB AD9512 STATUS STATUS PDB PROGRAMMABLE 3 independent 1.2 GHz LVPECL outputs DIVIDERS AND DSYNC LVPECL PHASE ADJUST DETECT Additive output jitter 225 fs rms OUT0 SYNC /1, /2, /3... /31, /32 DSYNCB 2 independent 800 MHz/250 MHz LVDS/CMOS clock outputs OUT0B LVPECL Additive output jitter 275 fs rms OUT1 /1, /2, /3... /31, /32 Fine delay adjust on 1 LVDS/CMOS output OUT1B CLK1 LVPECL Serial control port CLK1B OUT2 /1, /2, /3... /31, /32 Space-saving 48-lead LFCSP OUT2B CLK2 LVDS/CMOS CLK2B OUT3 /1, /2, /3... /31, /32 OUT3B SCLK APPLICATIONS SERIAL LVDS/CMOS SDIO CONTROL OUT4 Low jitter, low phase noise clock distribution SDO PORT /1, /2, /3... /31, /32 T OUT4B CSB Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs DELAY ADJUST High performance wireless transceivers High performance instrumentation Figure 1. Broadband infrastructure GENERAL DESCRIPTION The AD9512 provides a multi-output clock distribution in a One of the LVDS/CMOS outputs features a programmable design that emphasizes low jitter and low phase noise to delay element with a range of up to 10 ns of delay. This fine maximize data converter performance. Other applications with tuning delay block has 5-bit resolution, giving 32 possible demanding phase noise and jitter requirements can also benefit delays from which to choose. from this part. The AD9512 is ideally suited for data converter clocking There are five independent clock outputs. Three outputs are applications where maximum converter performance is LVPECL (1.2 GHz), and two are selectable as either LVDS achieved by encode signals with subpicosecond jitter. (800 MHz) or CMOS (250 MHz) levels. The AD9512 is available in a 48-lead LFCSP and can be Each output has a programmable divider that may be bypassed operated from a single 3.3 V supply. The temperature range is or set to divide by any integer up to 32. The phase of one clock 40C to +85C. output relative to another clock output may be varied by means of a divider phase select function that serves as a coarse timing adjustment. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 20052020 Analog Devices, Inc. All rights reserved. 05287-001AD9512 TABLE OF CONTENTS Specifications .................................................................................... 4 Outputs ........................................................................................ 30 Clock Inputs .................................................................................. 4 Power-Down Modes .................................................................. 31 Clock Outputs ............................................................................... 4 Chip Power-Down or Sleep ModePDB .......................... 31 Timing Characteristics ................................................................ 5 Distribution Power-Down .................................................... 31 Clock Output Phase Noise .......................................................... 7 Individual Clock Output Power-Down .............................. 31 Clock Output Additive Time Jitter .......................................... 10 Individual Circuit Block Power-Down ............................... 31 Serial Control Port ..................................................................... 12 Reset Modes ................................................................................ 31 FUNCTION Pin ......................................................................... 13 Power-On ResetStart-Up Conditions when VS is Applied .................................................................................... 31 SYNC STATUS Pin .................................................................... 13 Asynchronous Reset via the FUNCTION Pin ................... 31 Power ........................................................................................... 14 Soft Reset via the Serial Port ................................................. 31 Timing Diagrams ............................................................................ 15 Single-Chip Synchronization ................................................... 32 Absolute Maximum Ratings ......................................................... 16 SYNCBHardware SYNC ................................................... 32 Thermal Characteristics ............................................................ 16 Soft SYNCRegister 58h<2> .............................................. 32 ESD Caution................................................................................ 16 Multichip Synchronization ....................................................... 32 Pin Configuration and Function Descriptions .......................... 17 Serial Control Port ......................................................................... 33 Terminology .................................................................................... 19 Serial Control Port Pin Descriptions ....................................... 33 Typical Performance Characteristics ........................................... 20 General Operation of Serial Control Port .............................. 33 Functional Description .................................................................. 24 Framing a Communication Cycle with CSB ...................... 33 Overall .......................................................................................... 24 Communication CycleInstruction Plus Data ................ 33 FUNCTION Pin ......................................................................... 24 Write ........................................................................................ 33 RESETB: 58h<6:5> = 00b (Default) ..................................... 24 Read ......................................................................................... 34 SYNCB: 58h<6:5> = 01b ....................................................... 24 The Instruction Word (16 Bits) ............................................... 34 PDB: 58h<6:5> = 11b ............................................................. 24 MSB/LSB First Transfers ........................................................... 34 DSYNC and DSYNCB Pins ...................................................... 24 Register Map and Description ...................................................... 37 Clock Inputs ................................................................................ 24 Summary Table .......................................................................... 37 Dividers ........................................................................................ 25 Register Map Description ......................................................... 39 Setting the Divide Ratio ........................................................ 25 Power Supply .................................................................................. 43 Setting the Duty Cycle ........................................................... 25 Power Management ................................................................... 43 Divider Phase Offset .............................................................. 29 Applications .................................................................................... 44 Delay Block .................................................................................. 30 Using the AD9512 Outputs for ADC Clock Applications ... 44 Calculating the Delay ............................................................. 30 CMOS Clock Distribution ........................................................ 44 Rev. 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