2.5 V to 5.5 V, 115 A, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs AD5330/AD5331/AD5340/AD5341 FEATURES GENERAL DESCRIPTION 1 AD5330: single 8-bit DAC in 20-lead TSSOP The AD5330/AD5331/AD5340/AD5341 are single 8-/10-/12- AD5331: single 10-bit DAC in 20-lead TSSOP bit DACs. They operate from a 2.5 V to 5.5 V supply consuming AD5340: single 12-bit DAC in 24-lead TSSOP just 115 A at 3 V and feature a power-down mode that further AD5341: single 12-bit DAC in 20-lead TSSOP reduces the current to 80 nA. The devices incorporate an on-chip Low power operation: 115 A 3 V, 140 A 5 V output buffer that can drive the output to both supply rails, but PD Power-down to 80 nA 3 V, 200 nA 5 V via Pin the AD5330, AD5340, and AD5341 allow a choice of buffered 2.5 V to 5.5 V power supply or unbuffered reference input. Double-buffered input logic The AD5330/AD5331/AD5340/AD5341 have a parallel Guaranteed monotonic by design over all codes CS interface. selects the device and data is loaded into the Buffered/unbuffered reference input options input registers on the rising edge of WR. Output range: 0 V to V or 0 V to 2 V REF REF Power-on reset to 0 V The GAIN pin allows the output range to be set at 0 V to VREF or LDAC Simultaneous update of DAC outputs via pin 0 V to 2 VREF. CLR Asynchronous facility Input data to the DACs is double-buffered, allowing simultane- Low power parallel data interface LDAC ous update of multiple DACs in a system using the pin. On-chip rail-to-rail output buffer amplifiers CLR An asynchronous input is also provided, which resets the Temperature range: 40C to +105C contents of the input register and the DAC register to all zeros. APPLICATIONS These devices also incorporate a power-on reset circuit that Portable battery-powered instruments ensures that the DAC output powers on to 0 V and remains Digital gain and offset adjustment there until valid data is written to the device. Programmable voltage and current sources The AD5330/AD5331/AD5340/AD5341 are available in thin Programmable attenuators shrink small outline packages (TSSOP). Industrial process control 1 Protected by U.S. Patent Number 5,969,657. FUNCTIONAL BLOCK DIAGRAM V V REF DD 3 12 POWER-ON RESET AD5330 BUF 1 INPUT DAC GAIN 8 REGISTER REGISTER 8-BIT DB 20 BUFFER 4 7 V . OUT . DAC DB 13 0 6 CS 7 WR RESET POWER-DOWN 9 CLR LOGIC 10 LDAC 11 5 PD GND Figure 1. AD5330 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20002008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. INTERFACE LOGIC 06852-001AD5330/AD5331/AD5340/AD5341 TABLE OF CONTENTS Features .............................................................................................. 1 Double-Buffered Interface ........................................................ 18 Applications ....................................................................................... 1 Clear Input (CLR) ...................................................................... 18 General Description ......................................................................... 1 Chip Select Input (CS) ............................................................... 18 Functional Block Diagram .............................................................. 1 Write Input (WR) ....................................................................... 18 Revision History ............................................................................... 2 LDAC Load DAC Input ( ) .......................................................... 18 Specif icat ions ..................................................................................... 3 High-Byte Enable Input (HBEN) ............................................. 18 AC Characteristics ........................................................................ 4 Power-On Reset .......................................................................... 18 Timing Characteristics ................................................................ 5 Power-Down Mode ........................................................................ 19 Absolute Maximum Ratings ............................................................ 6 Suggested Databus Formats .......................................................... 20 ESD Caution .................................................................................. 6 Applications Information .............................................................. 21 Pin Configurations and Function Descriptions ........................... 7 Typical Application Circuits ..................................................... 21 Terminology .................................................................................... 11 Driving VDD From the Reference Voltage ............................... 21 Typical Performance Characteristics ........................................... 13 Bipolar Operation Using the AD5330/AD5331/ Theory of Operation ...................................................................... 17 AD5340/AD5341 ......................................................................... 21 Digital-to-Analog Section ......................................................... 17 Decoding Multiple AD5330/AD5331/ AD5340/AD5341 .... 21 Resistor String ............................................................................. 17 Programmable Current Source ................................................ 22 DAC Reference Input ................................................................. 17 Power Supply Bypassing and Grounding ................................ 22 Output Amplifier ........................................................................ 17 Outline Dimensions ....................................................................... 24 Parallel Interface ............................................................................. 18 Ordering Guide .......................................................................... 25 REVISION HISTORY 2/08Rev. 0 to Rev. A Updated Format .................................................................. Universal Changes to Table 4 .......................................................................... 16 Replaced Driving V from the Reference Voltage Section ..... 21 DD Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 25 4/00Revision 0: Initial Version Rev. A Page 2 of 28