Apacer Memory Product Specification 1024MB DDR2 SDRAM SO-DIMM 1024MB DDR2 SDRAM SO-DIMM based on 128Mx8 ,8Banks, 1.8V DDR2 SDRAM with SPD Features ( Bandwidth: 6.4 GB/sec ) Performance range Part Number Max Freq. (Clock) Speed Grade 78.02G86.XX2 400MHz(2.5ns CL6) 800Mbps JEDECstandard 1.8V 0.1V Power Supply VDDQ = 1.8V 0.1V Internal Bank: 8 Bank Posted CAS Programmable CAS Latency: 3, 4, 5 Programmable Additive Latency: 0, 1 , 2 , 3 and 4 Write Latency(WL) = Read Latency(RL) -1 Burst Length: 4 , 8(Interleave/nibble sequential) Programmable Sequential / Interleave Burst Mode Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature) Off-Chip Driver(OCD) Impedance Adjustment On Die Termination Refresh and Self Refresh Average Refesh Period 7.8us Serial presence detect with EEPROM Compliance with RoHS Compliance with CE Operating Temperature Rang: Commercial 0C TC 85C Industrial -40C TA 85C Refresh: auto-refresh, self-refresh Average refresh period 7.8us at 0C TC 85C 3.9us at 85C TC 95C Industrial System Level -40C TA 70C Description This module is 128M bit x 64 x1Rank Double Data Rate SDRAM high density memory modules based on first generation of 1024MB DDR2 SDRAM respectively. It consists of eight CMOS 128M x 8 bit with 8banks Double Data Rate SDRAMs in 60Ball FBGA packages mounted on a 200pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR2 SDRAM. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.Apacer Memory Product Specification Pin Configurations (Front side/Back side) Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back V V 1 2 51 DQS2 52 DM2 101 A1 102 A0 151 DQ42 152 DQ46 REF SS V V V V V 3 4DQ4 53 54 103 104 153 DQ43 154 DQ47 SS SS SS DD DD 5 DQ0 6 DQ5 55 DQ18 56 DQ22 105 A10/AP 106 BA1 155 V 156 V SS SS 7DQ18 V 57 DQ19 58 DQ23 107 BA0 108 RAS 157 DQ48 158 DQ52 SS 9 V 10 DM0 59 V 60 V 109 WE 110 S0 159 DQ49 160 DQ53 SS SS SS V V V V V 11 DQS012 61 DQ24 62 DQ28 111 112 161 162 SS DD DD SS SS 13 DQS0 14 DQ6 63DQ2564DQ29 113 CAS 114 ODT0 163 NC, TEST 164 CK1 V V V V 15 16 DQ7 65 66 115 NC/S1 116 A13 165 166 CK1 SS SS SS SS V V V V 17 DQ2 18 67 DM3 68 DQS3117 118 167 DQS6 168 SS DD DD SS 19 DQ3 20 DQ12 69 NC 70 DQS3 119 NC/ODT1 120 NC 169 DQS6 170 DM6 V V V V V V V 21 22 DQ13 71 72 121 122 171 172 SS SS SS SS SS SS SS 23 DQ8 24 V 73 DQ26 74 DQ30 123 DQ32 124 DQ36 173 DQ50 174 DQ54 SS 25 DQ9 26 DM1 75 DQ27 76 DQ31 125 DQ33 126 DQ37 175 DQ51 176 DQ55 27 V 28 V 77 V 78 V 127 V 128 V 177 V 178 V SS SS SS SS SS SS SS SS 29 DQS1 30 CK0 79 CKE0 80 NC/CKE1 129 DQS4 130 DM4 179 DQ56 180 DQ60 31 DQS1 32 CK081 V 82 V 131DQS4132 V 181 DQ57 182 DQ61 DD DD SS 33 V 34 V 83 NC 84 NC 133 V 134DQ38183 V 184 V SS SS SS SS SS 35 DQ10 36 DQ14 85 BA2 86 NC 135 DQ34 136 DQ39 185 DM7 186 DQS7 V V V V 37 DQ11 38 DQ15 87 88 137DQ35138 187 188 DQS7 DD DD SS SS V V V V 39 40 89 A12 90 A11 139 140 DQ44 189 DQ58 190 SS SS SS SS V V 41 42 91 A9 92 A7 141 DQ40 142 DQ45 191 DQ59 192 DQ62 SS SS V V 43 DQ16 44 DQ20 93 A8 94 A6 143 DQ41 144 193 194 DQ63 SS SS 45 DQ17 46 DQ21 95 V 96 V 145 V 146 DQS5 195 SDA 196 V DD DD SS SS 47 V 48 V 97 A5 98 A4 147 DM5 148 DQS5 197 SCL 198 SA0 SS SS 49 DQS250 NC 99 A3 100 A2 149 V 150 V 199 V SPD 200 SA1 SS SS DD Pin Description Pin Name Function Pin Name Function CK0,CK1 Clock Inputs, positive line SDA SPD Data Input/Output CK0,CK1 Clock Inputs, negative line SA1,SA0 SPD address CKE0,CKE1 Clock Enables DQ0~DQ63 Data Input/Output RAS Row Address Strobe DM0~DM7 Data Masks CAS Column Address Strobe DQS0~DQS7 Data strobes WE Write Enable DQS0~DQS7 Data strobes complement Logic Analyzer specific test pin (No connect on S0,S1 Chip Selects TEST So-DIMM) V A0~A9, A11~A13 Address Inputs Core and I/O Power DD V A10/AP Address Input/Autoprecharge Ground SS BA0-BA2 SDRAM Bank Address V Input/Output Reference REF ODT0,ODT1 On-die termination control V SPD SPD Power DD SCL Serial Presence Detect(SPD) Clock Input NC Spare pins, No connect