W25N02KVxxIR/U 3V 2G-BIT SLC QSPINAND FLASH MEMORY WITH DUAL/QUAD SPI BUFFER READ & SEQUENTIAL READ Publication Release Date: June 25, 2021 Revision G W25N02KVxxIR/U Table of Contents 1. GENERAL DESCRIPTIONS ............................................................................................................. 6 2. FEATURES ....................................................................................................................................... 6 3. PACKAGE TYPES AND PIN CONFIGURATIONS .......................................................................... 7 3.1 Pad Configuration WSON 8x6-mm ...................................................................................... 7 3.2 Pad Description WSON 8x6-mm .......................................................................................... 7 3.3 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) ................................................. 8 3.4 Ball Description TFBGA 8x6-mm ......................................................................................... 8 4. PIN DESCRIPTIONS ........................................................................................................................ 9 4.1 Chip Select (/CS) .................................................................................................................. 9 4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) .................................... 9 4.3 Write Protect (/WP) ............................................................................................................... 9 4.4 HOLD (/HOLD) ..................................................................................................................... 9 4.5 Serial Clock (CLK) ................................................................................................................ 9 5. BLOCK DIAGRAM .......................................................................................................................... 10 6. FUNCTIONAL DESCRIPTIONS ..................................................................................................... 11 6.1 Device Operation Flow ....................................................................................................... 11 6.1.1 Standard SPI Instructions ..................................................................................................... 11 6.1.2 Dual SPI Instructions ............................................................................................................ 11 6.1.3 Quad SPI Instructions ........................................................................................................... 12 6.1.4 Hold Function ........................................................................................................................ 12 6.2 Write Protection .................................................................................................................. 13 7. PROTECTION, CONFIGURATION AND STATUS REGISTERS .................................................. 14 7.1 Protection Register / Status Register-1 (Volatile Writable, OTP lockable) ......................... 14 7.1.1 Block Protect Bits (BP3, BP2, BP1, BP0, TB) Volatile Writable, OTP lockable .................. 14 7.1.2 Write Protection Enable Bit (WP-E) Volatile Writable, OTP lockable ................................. 15 7.1.3 Status Register Protect Bits (SRP1, SRP0) Volatile Writable, OTP lockable ..................... 15 7.2 Configuration Register / Status Register-2 (Volatile Writable) ........................................... 16 7.2.1 One Time Program Lock Bit (OTP-L) OTP lockable .......................................................... 16 7.2.2 Enter OTP Access Mode Bit (OTP-E) Volatile Writable ..................................................... 16 7.2.3 Status Register-1 Lock Bit (SR1-L) OTP lockable ............................................................. 16 7.2.4 ECC Enable Bit (ECC-E) Volatile Writable ......................................................................... 17 7.2.5 Output Driver Strength (ODS-1, ODS-0) Volatile Writable ................................................. 19 7.2.6 Hold Disable (H-DIS) Volatile Writable............................................................................... 19 7.2.7 Buffer Read / Sequential Read Mode Bit (BUF) Volatile Writable ...................................... 19 7.3 Status Register-3 (Status Only) .......................................................................................... 20 7.3.1 Cumulative ECC Status (ECC-1, ECC-0) Status Only ....................................................... 20 7.3.2 Program Failure (P-FAIL) Status Only ............................................................................... 21 7.3.3 Erase Failure (E-FAIL) Status Only ................................................................................... 21 7.3.4 Write Enable Latch (WEL) Status Only .............................................................................. 21 7.3.5 Erase/Program In Progress (BUSY) Status Only ............................................................... 21 7.4 Extended internal ECC feature registers ............................................................................ 22 7.4.1 ECC Bit Flip Count Detection (BFD) Volatile Writable ....................................................... 22 Publication Release Date: June 25, 2021 - 1 - Revision G