STA32613TR STMicroelectronics

STA326 2.1-channel high-efficiency digital audio system Datasheet - production data Bass/treble tone control Dual independent programmable limiters/compressors Automodes 32 preset EQ curves 15 preset crossover settings Auto volume-controlled loudness 3 preset volume curves 2 preset anti-clipping modes PowerSO-36 with exposed pad up Preset nighttime listening mode Preset TV AGC Input and output channel mapping AM noise-reduction and PWM Features frequency-shifting modes Wide supply voltage range (10 V - 36 V) Software volume update and muting Three power output configurations Auto zero detect and invalid input detect 2 x 40 W + 1 x 80 W muting 2 x 80 W Selectable DDX ternary or binary PWM 1 x 160 W output + variable PWM speeds PowerSO-36 package (exposed pad up (EPU)) Selectable de-emphasis 2.1 channels of 24-bit DDX Post-EQ user-programmable mix with default 2.1 bass-management settings 100-dB SNR and dynamic range Variable max power correction for lower full- 32 kHz to 192 kHz input sample rates power THD Digital gain/attenuation +48 dB to -80 dB in Four output routing configurations 0.5-dB steps Selectable clock input ratio Four 28-bit user-programmable biquads (EQ) per channel 96 kHz internal processing sample rate, 24 to 2 28-bit precision I C control 2 Video application supports 576 * fs input mode 2-channel I S input data interface Individual channel and master gain/attenuation Individual channel and master soft/hard mute Individual channel volume and EQ bypass Table 1. Device summary Order code Package Packaging STA32613TR PowerSO-36 EPU Tape and reel January 2016 DocID11531 Rev 9 1/64 This is information on a product in full production. www.st.com Obsolete Product(s) - Obsolete Product(s)Contents STA326 Contents 1 Description . 8 1.1 EQ processing 9 1.2 Output configurations . 9 2 Pin out . 10 2.1 Package pins 10 2.2 Pin list 10 2.3 Pin description . 12 3 Electrical specifications . 13 3.1 General interface specifications 13 3.2 DC electrical specifications (3.3 V buffers) 14 3.3 Power electrical specifications . 14 4 Power supply and control sequencing . 16 5 Characterization curves . 17 2 6I C bus specification 19 6.1 Communication protocol 19 6.2 Device addressing 19 6.3 Write operation . 20 6.4 Read operation . 20 7 Register description 22 7.1 Configuration register A (addr 0x00) 23 7.2 Configuration register B (addr 0x01) 26 7.3 Configuration register C (addr 0x02) 29 7.3.1 DDX power output mode . 29 7.3.2 DDX variable compensating pulse size 29 7.4 Configuration register D (addr 0x03) 30 7.5 Configuration register E (addr 0x04) 32 7.6 Configuration register F (addr 0x05) 34 2/64 DocID11531 Rev 9 Obsolete Product(s) - Obsolete Product(s)