Si5315 SYNCHRONOUS ETHERNET/TELECOM JITTER ATTENUATING CLOCK MULTIPLIER Features Provides jitter attenuation and frequency Selectable loop bandwidth for jitter translation between SONET/PDH and attenuation: 60 to 8.4 kHz Ethernet Automatic/Manual hitless switching Supports ITU-T G.8262 Synchronous and holdover during loss of inputs Ethernet equipment slave clock (EEC clock option 1 and 2) requirements with Programmable output clock signal optional Stratum 3 compliant timing card format: LVPECL, LVDS, CML or clock source CMOS Two clock inputs/two clock outputs 40 MHz crystal or XO reference Input frequency range: 8 kHz644 MHz Single supply: 1.8, 2.5, or 3.3 V Output frequency range: 8 kHz644 MHz On-chip voltage regulator with high Ultra low jitter: PSRR 0.23 ps RMS (1.87520 MHz) Loss of lock and loss of signal alarms Ordering Information: 0.47 ps RMS (12 kHz20 MHz) Small size: 6 x 6 mm, 36-QFN Simple pin control interface Wide temperature range: 40 to See page 48. +85 C Applications Pin Assignments Synchronous Ethernet line cards Carrier Ethernet switches routers SONET OC-3/12/48 line cards MSAN / DSLAM PON OLT/ONU T1/E1/DS3/E3 line cards Description 36 35 34 33 32 31 30 29 28 RST 1 27 FRQSEL3 The Si5315 is a jitter-attenuating clock multiplier for Gb and 10G Synchronous FRQTBL 2 26 FRQSEL2 LOS1 3 25 FRQSEL1 Ethernet, SONET/SDH, and PDH (T1/E1) applications. The Si5315 supports SyncE LOS2 4 24 FRQSEL0 EEC options 1 and 2 when paired with a timing card that implements the required GND VDD 5 23 BWSEL1 wander filter. The Si5315 accepts dual clock inputs ranging from 8 kHz to 644.53 MHz Pad XA 6 22 BWSEL0 and generates two equal frequency-multiplied clock outputs ranging from 8 kHz to XB 7 21 CS CA 644.53 MHz. The input clock frequency and clock multiplication ratio are selectable GND 8 20 GND from a table of popular SyncE and T1/E1 rates. The Si5315 is based on Skyworks AUTOSEL 9 19 GND 10 11 12 13 14 15 16 17 18 Solutions third-generation DSPLL technology, which provides any-frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is user programmable, providing jitter performance optimization at the application level. Functional Block Diagram XTAL/Clock Si5315 Clock Out 1 Clock In 1 Output Signal Format 1:0 DSPLL Clock In 2 Clock Out 2 Clock 2 Disable/PLL Bypass Loss of Lock Loss of Signal 1 Status/Control VDD (1.8, 2.5, or 3.3 V) Loss of Signal 2 GND Frequency Select 3:0 Manual/Auto Clock Selection Frequency Table Select Clock Switch/Clock Active Indicator Loop Bandwidth Select 1:0 XTAL/Clock Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 1.0 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice August 23, 2021 VDD NC XTAL/CLOCK CKOUT2+ CKIN2+ CKOUT2 CKIN2 SFOUT0 DBL2 BY VDD GND GND CKIN1+ SFOUT1 CKIN1 CKOUT1 LOL CKOUT1+Si5315 2 Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 1.0 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice August 23, 2021