VEE 2:1 Differential-to-LVPECL Multiplexer 853S01 Datasheet General Description Features The 853S01 is a high performance 2:1 Differential-to-LVPECL One LVPECL output pair Multiplexer. The 853S01 can also perform differential translation Two selectable differential LVPECL clock inputs because the differential inputs accept LVPECL, LVDS and CML PCLKx, nPCLKx pairs can accept the following levels. The 853S01 is packaged in a small 3mm x 3mm 16 VFQFN differential input levels: LVPECL, LVDS, CML package, making it ideal for use on space constrained boards. Translates LVCMOS/LVTTL input signals to LVPECL levels by using a resistor bias network on nPCLKx, nPCLKx Part-to-part skew: 150ps (maximum) Propagation delay: 490ps (maximum) Full 3.3V or 2.5V operating supply -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) packages Block Diagram Pin Assignments Pulldown PCLK0 0 Pullup/Pulldown nPCLK0 Q 16 15 14 13 PCLK0 1 12 VEE nQ Pulldown PCLK1 1 Pullup/Pulldown 2 nPCLK0 11 Q nPCLK1 3 PCLK1 10 nQ Pulldown CLK SEL nPCLK1 4 9 VEE 5 6 7 8 V BB ICS853S01I 16-Lead VFQFN 3mm x 3mm x 0.925mm package body K Package Top View PCLK0 1 16 nc 2 15 VEE nPCLK0 PCLK1 3 14 VEE nPCLK1 4 13 VCC VBB 5 12 VEE CLK SEL 6 11 Q nc 7 10 nQ VCC 8 9 853S01 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body G Package Top View 2016 Integrated Device Technology, Inc. 1 Revision B, March 4, 2016 VBB nc CLK SEL VEE nc VEE VCC VCC853S01 Datasheet Table 1. Pin Descriptions Number Name Type Description 1 PCLK0 Input Pulldown Non-inverting differential LVPECL clock input. Pullup/ 2 nPCLK0 Input Inverting differential LVPECL clock input. V /2 default when left floating. CC Pulldown 3 PCLK1 Input Pulldown Non-inverting differential LVPECL clock input. Pullup/ 4 nPCLK1 Input Inverting differential LVPECL clock input. V /2 default when left floating. CC Pulldown 5V Output Bias voltage. BB Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs. When 6 CLK SEL Input Pulldown LOW, selects PCLK0, nPCLK0 inputs. LVCMOS/LVTTL interface levels. 7, 16 nc Unused No connect. 8, 13 V Power Positive supply pins. CC 9, 12, 14, 15 V Power Negative supply pins. EE 10, 11 nQ, Q Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 2 pF IN Input Pulldown Resistor 37 k R PULLDOWN R Input Pullup Resistor 37 k PULLUP Function Tables Table 3. Control Input Function Table CLK SEL Input Selected 0 PCLK0, nPCLK0 1 PCLK1, nPCLK1 2016 Integrated Device Technology, Inc. 2 Revision B, March 4, 2016