CLK0 Low Skew, 1-to-5, Differential-to-3.3V 85304-01 Data Sheet LVPECL Fanout Buffer General Description Features The 85304-01 is a low skew, high performance 1-to-5 Five 3.3V differential LVPECL output pairs Differential-to-3.3V LVPECL fanout buffer. The 85304-01 has two Selectable differential CLKx, nCLKx input pairs selectable clock inputs. The CLKx, nCLKx pairs can accept most CLKx, nCLKx input pairs can accept the following differential standard differential input levels. The clock enable is internally levels: LVDS, LVPECL, LVHSTL, SSTL and HCSL levels synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/ deassertion of the clock enable pin. Maximum output frequency: 650MHz Guaranteed output and part-to-part skew characteristics make the Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nCLKx inputs 85304-01 ideal for those applications demanding well defined performance and repeatability. Output skew: 35ps (maximum) Part-to-part skew: 150ps (maximum) Propagation delay: 2.1ns (maximum) Full 3.3V supply mode 0C to 70C ambient operating temperature Block Diagram Pin Assignment Q0 1 20 VCC Pullup CLK EN nQ0 2 19 CLK EN D Q1 3 18 VCC Q nQ1 4 17 nCLK1 LE Pulldown CLK0 Q2 5 16 CLK1 Pullup 0 0 Q0 nCLK0 nQ2 6 15 VEE nQ0 Pulldown Q3 CLK1 7 14 nCLK0 1 Pullup 1 nCLK1 nQ3 8 13 Q1 Q4 9 12 CLK SEL nQ1 Pulldown CLK SEL nQ4 10 11 VCC Q2 nQ2 85304-01 Q3 20-Lead TSSOP nQ3 6.5mm x 4.4mm x 0.925mm Q4 package body nQ4 G Package Top View 2015 Integrated Device Technology, Inc 1 Revision E December 2, 201585304-01 Data Sheet Table 1. Pin Descriptions Number Name Type Description 1, 2 Output Differential output pair. LVPECL interface levels. Q0, nQ0 3, 4 Output Differential output pair. LVPECL interface levels. Q1, nQ1 5, 6 Output Differential output pair. LVPECL interface levels. Q2, nQ2 7, 8 Output Differential output pair. LVPECL interface levels. Q3, nQ3 9, 10 Output Differential output pair. LVPECL interface levels. Q4, nQ4 Power Power supply pins. 11, 18, 20 V CC Clock select input. When HIGH, selects CLK1, nCLK1 inputs. When LOW, 12 CLK SEL Input Pulldown selects CLK0, nCLK0 inputs. LVTTL/LVCMOS interface levels. 13 CLK0 Input Pulldown Non-inverting differential clock input. 14 nCLK0 Input Pullup Inverting differential clock input. 15 V Power Negative supply pin. EE 16 CLK1 Input Pulldown Non-inverting differential clock input. 17 nCLK1 Input Pullup Inverting differential clock input. Synchronizing clock enable. When HIGH, clock outputs follow clock input. 19 CLK EN Input Pullup When LOW, Qx outputs are forced LOW, nQx outputs are forced HIGH. LVTTL/LVCMOS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pulldown Resistor 51 k PULLDOWN Input Pullup Resistor 51 k R PULLUP 2015 Integrated Device Technology, Inc 2 Revision E December 2, 2015