ACT88327 Advanced PMIC with 3 Bucks, 2 LDOs, and Load Bypass Switches BENEFITS and FEATURES GENERAL DESCRIPTION TM The ACT88327 PMIC is an integrated ActiveCiPS Wide input voltage range power management integrated circuit. It powers a wide Vin = 2.7V to 5.5V range of processors, including solid-state drive applica- Complete integrated power solution tions, video processors, FPGAs, wearables, periph- One 2A avg / 3A peak DC/DC Step-Down (Buck) erals, and microcontrollers. The ACT88327 is optimized Regulator with Bypass Function for SSD and FPGA applications. It is highly flexible and 2 can be reconfigured via I C for multiple applications One 2A avg / 3A peak DC/DC Step-Down (Buck) without the need for PCB changes. The low external Regulator component count and high configurability significantly One 1A avg / 1.5A peak DC/DC Step-Down speeds time to market. Examples of configurable op- (Buck) tions include output voltage, startup time, slew rate, sys- Regulator2 tem level sequencing, switching frequency, sleep Two 300mA LDOs modes, operating modes etc. ACT88327 is pro- Space Savings grammed at the factory with a default configuration. These settings can be optimized for a specific design Fully integrated 2 through the I C interface. The ACT88327 is available in High Fsw =2.25MHz or 1.125MHz several default configuration. Contact the factory for Works with 0.47H Inductor specific default configurations. Integrated sequencing The core of the device includes three DC/DC step down Easy system level design converters using integrated power FETs, two low-drop- Configurable sequencing out regulators (LDOs). Buck1 and LDO1 can be config- Multiple Wake up Triggers with GPIOs ured as a load switch. Each DC/DC regulator switches at either 1.125MHz or 2.25MHz, requiring only three Seven Programmable GPIOs small components for operation. The LDOs only require Buck 1 Bypass Mode for 3.3V system level small ceramic capacitors. All are highly configurable via compliance 2 the I C interface. Highly configurable The ACT88327 PMIC is available in a 2.18 x 2.581 mm uP interface for status reporting and controllability 30 ball WLCSP package. Programmable Reset and Power Good GPIOs Flexible Sequencing Options Multiple Sleep Modes 2 I C Interface 1MHz APPLICATIONS Solid-State Drives (SSD) FPGA Computer Vision Portable Audio / Video Datasheet Rev. A, May 25, 2020 Subject to change without notice 1 of 50 www.qorvo.com ACT88327 Advanced PMIC with 3 Bucks, 2 LDOs, and Load Bypass Switches TYPICAL APPLICATION DIAGRAM BUCK1 3A 2.7V ~ 5.5V Input BUCK2 3A BUCK3 1.5A ACT88327 SOC PG External LDO1 300mA DC/DC 1A Load Switch ENABLE LDO2 300mA SCL SDA GPIOs Datasheet Rev. A May 25, 2020 Subject to change without notice 2 of 50 www.qorvo.com