NB4N855S Translator, 3.3 V, 1.5 Gb/s Dual AnyLevel to LVDS Receiver/Driver/Buffer Description NB4N855S D0 V 1 10 CC D0 Q0 2 9 D1 3 8 Q0 D1 4 7 Q1 GND 5 Q1 6 Figure 2. Pin Configuration and Block Diagram (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 1 D0 LVPECL, CML, LVCMOS, Noninverted Differential Clock/Data D0 Input. LVTTL, LVDS 2 D0 LVPECL, CML, LVCMOS, Inverted Differential Clock/Data D0 Input. LVTTL, LVDS 3 D1 LVPEL, CML, LVDS LVCMOS, Noninverted Differential Clock/Data D1 Input. LVTTL 4 D1 LVPECL, CML, LVDS Inverted Differential Clock/Data D1 Input. LVCMOS LVTTL 5 GND Ground. 0 V. 6 Q1 LVDS Output Inverted Q1 output. Typically loaded with 100 receiver termination resistor across differential pair. 7 Q1 LVDS Output Noninverted Q1 output. Typically loaded with 100 receiver termination resistor across differential pair. 8 Q0 LVDS Output Inverted Q0 output. Typically loaded with 100 receiver termination resistor across differential pair. 9 Q0 LVDS Output Noninverted Q0 output. Typically loaded with 100 receiver termination resistor across differential pair. 10 V Positive Supply Voltage. CC