NB4N121K
3.3V Differential 1:21
Differential Fanout Clock
Driver with HCSL level
Output
NB4N121K
Exposed Pad (EP)
VCC
I 39
1
REF
GND 2 38 Q6
Q6
VTCLK 3 37
CLK 36 Q7
4
Q7
CLK 5 35
VTCLK 6 34 Q8
V 7 NB4N121K 33 Q8
CC
Q20
8 32 Q9
9 31 Q9
Q20
Q19 10 30 Q10
Q19 11 29 Q10
12 28 Q11
Q18
13 27 Q11
Q18
Figure 2. Pinout Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin Name I/O Description
1 I Output Output current programming pin to select load drive. For 1X
REF
configuration, connect I to GND, or for 2X configuration, connect
REF
I to V (See Figure 9).
REF CC
2 GND Supply Ground. GND pin must be externally connected to power supply
to guarantee proper operation.
3, 6 VTCLK, Internal 50 Termination Resistor connection Pins. In the differential
VTCLK
configuration when the input termination pins are connected to the com-
mon termination voltage, and if no signal is applied then the device may
be susceptible to selfoscillation.
4 CLK LVPECL Input CLOCK Input (TRUE)
5 CLK LVPECL Input CLOCK Input (INVERT)
7, 26, 39, 52 V Positive Supply pins. V pins must be externally connected to a power
CC CC
supply to guarantee proper operation.
8, 10, 12, 14, 16, 18, 20, 22, Q[200] HCSL Output Output (INVERT)
24, 27, 29, 31, 33, 35, 37, 40,
42, 44, 46, 48, 50
9, 11, 13, 15, 17, 19, 21, 23, Q[200] HCSL Output Output (TRUE)
25, 28, 30, 32, 34, 36, 38, 41,
43, 45, 47, 49, 51
Exposed Pad EP GND Exposed Pad. The thermally exposed pad (EP) on package bottom (see
case drawing) must be attached to a sufficient heatsinking conduit for
proper thermal operation. (Note 1)
1. The exposed pad must be connected to the circuit board ground.