74LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear
January 2008
74LVTH273
Low Voltage Octal D-Type Flip-Flop with Clear
Features General Description
Input and output interface capability to systems at The LVTH273 is a high-speed, low-power positive-edge-
5V V triggered octal D-type flip-flop featuring separate D-type
CC
inputs for each flip-flop. A buffered Clock (CP) and Clear
Bushold on the data inputs eliminate the need for
(CLR) are common to all flip-flops.
external pull-up resistors to hold unused inputs
Outputs source/sink 32mA/+64mA
The state of each D-type input, one setup time before
the positive clock transition, is transferred to the corre-
Functionally compatible with the 74 series 273
sponding flip-flop's output.
Latch-up performance exceeds 500mA
ESD performance: The LVTH273 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
Human-body model > 2000V
inputs.
Machine model > 200V
These octal flip-flops are designed for low-voltage (3.3V)
Charged-device model > 1000V
V
applications, but with the capability to provide a TTL
CC
interface to a 5V environment. The LVTH273 is fabri-
cated with an advanced BiCMOS technology to achieve
high speed operation similar to 5V ABT while maintain-
ing low power dissipation.
Ordering Information
Package
Order Number Number Package Description
74LVTH273WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LVTH273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVTH273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
1999 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LVTH273 Rev. 1.6.074LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear
Connection Diagram
Logic Symbols
IEEE/IEC
Pin Description
Pin Names Description
D D Data Inputs
0 7
CP Clock Pulse Input
CLR Clear
O O Outputs
0 7
Truth Table
Inputs Outputs
Functional Description
D CP CLR O
n n
The LVTH273 consists of eight positive-edge-triggered
HH H
flip-flops with individual D-type inputs. The buffered
LH L
Clock and Clear are common to all flip-flops. The eight
flip-flops will store the state of their individual D-type
XH or L H O
o
inputs that meet the setup and hold time requirements
XX L L
on the LOW-to-HIGH Clock (CP) transition. When the
H = HIGH Voltage Level
Clock is either HIGH or LOW, the D-input signal has no
effect at the output. When the Clear (CLR) is LOW, all
L = LOW Voltage Level
Outputs will be forced LOW.
X = Immaterial
= LOW-to-HIGH Transition
O = Previous O before HIGH-to-LOW of CP
o o
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
1999 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LVTH273 Rev. 1.6.0 2