74LVC86APW,118 Nexperia

74LVC86A Quad 2-input EXCLUSIVE-OR gate Rev. 5 19 October 2011 Product data sheet 1. General description The 74LVC86A provides four 2-input EXCLUSIVE-OR functions. It is a high-performance, low power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. 2. Features and benefits 5 V tolerant inputs for interlacing with 5 V logic Supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Direct interface with TTL levels Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from 40 C to +85 C and 40 C to 125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC86AD 40 Cto +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74LVC86ADB 40 Cto +125 C SSOP14 plastic shrink small outline package 14 leads SOT337-1 body width 5.3 mm 74LVC86APW 40 Cto +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74LVC86ABQ 40 Cto +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package no leads 14 terminals body 2.5 3 0.85 mm74LVC86A NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate 4. Functional diagram 1 =1 3 2 4 1 1A =1 6 1Y 3 5 2 1B 4 2A 2Y 6 5 2B 9 =1 8 9 3A 10 3Y 8 10 3B 12 4A 12 4Y 11 =1 13 4B 11 13 mna787 mna786 Fig 1. Logic symbol Fig 2. IEC logic symbol A Y B mna788 Fig 3. Logic diagram for one gate 74LVC86A All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 19 October 2011 2 of 15