74LV259 8-bit addressable latch Rev. 03 2 January 2008 Product data sheet 1. General description The 74LV259 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC259 and 74HCT259. The 74LV259 is a high-speed 8-bit addressable latch designed for general purpose storage applications in digital systems. The 74LV259 is multifunctional device capable of storing single-line data in eight addressable latches, and also 3-to-8 decoder and demultiplexer, with active HIGH outputs (Q0 to Q7), functions are available. The 74LV259 also incorporates an active LOW common reset (MR) for resetting all latches, as well as, an active LOW enable input (LE). The 74LV259 has four modes of operation as shown in the mode select table. In the addressable latch mode, data on the data line (D) is written into the addressed latch. The addressed latch will follow the data input with all non-addressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the state of the (D) input with all other outputs in the LOW state. In the reset mode all outputs are LOW and unaffected by the address (A0 to A2) and data (D) input. When operating the 74LV259 as an address latch, changing more than one bit of address could impose a transient-wrong address. Therefore, this should only be done while in the memory mode. 2. Features Optimized for low voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between V = 2.7 V and V = 3.6 V CC CC Typical output ground bounce < 0.8 V at V = 3.3 V and T = 25 C CC amb Typical HIGH-level output voltage (V ) undershoot: > 2 V at V = 3.3 V and OH CC T =25 C amb Combines demultiplexer and 8-bit latch Serial-to-parallel capability Output from each storage bit available Random (addressable) data entry Easily expandable Common reset input Useful as a 3-to-8 active HIGH decoder ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specied from - 40 Cto+85 C and from - 40 C to +125 C74LV259 NXP Semiconductors 8-bit addressable latch 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV259N - 40 C to +125 C DIP16 plastic dual in-line package 16 leads (300 mil) SOT38-4 74LV259D - 40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74LV259DB - 40 C to +125 C SSOP16 plastic shrink small outline package 16 leads SOT338-1 body width 5.3 mm 74LV259PW - 40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74LV259BQ - 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced very SOT763-1 thin quad at package no leads 16 terminals body 2.5 3.5 0.85 mm 4. Functional diagram 15 G8 13 Z9 9,10D DX 14 1 C10 4 0 8R LE 1 0 Q0 4 5 1 2 0 G 13 D Q1 5 3 7 6 2 Q2 6 2 14 Q3 7 7 3 1 A0 Q4 9 9 4 2 A1 Q5 10 3 A2 Q6 11 10 5 Q7 12 11 MR 6 12 7 15 001aah118 001aah119 Fig 1. Logic symbol Fig 2. IEC logic symbol 74LV259 3 NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 2 January 2008 2 of 19