Features Fast read access time 55ns Low-power CMOS operation 100A max standby 25mA max active at 5MHz JEDEC standard packages 32-lead PDIP 32-lead PLCC 5V 10% supply 2Mb (256K x 8) High-reliability CMOS technology One-time 2,000V ESD protection 200mA latchup immunity Programmable, Rapid programming algorithm 100s/byte (typical) Read-only Memory CMOS- and TTL-compatible inputs and outputs Integrated product identification code Industrial and automotive temperature ranges Atmel AT27C020 Green (Pb/halide-free) packaging option 1. Description The Atmel AT27C020 is a low-power, high-performance, 2,097,152-bit, one-time pro- grammable, read-only memory (OTP EPROM) organized as 256K by 8 bits. It requires only one 5V power supply in normal read mode operation. Any byte can be accessed in less than 55ns, eliminating the need for speed-reducing WAIT states on high-performance micropro- cessor systems. In read mode, the AT27C020 typically consumes 8mA. Standby mode supply current is typically less than 10A. The AT27C020 is available in a choice of industry-standard, JEDEC approved, one-time pro- grammable (OTP) PDIP and PLCC packages. All devices feature two-line control (CE, OE) to give designers the flexibility to prevent bus contention. With 256K byte storage capability, the AT27C020 allows firmware to be stored reliably and to be accessed by the system without the delays of mass storage media. The AT27C020 has additional features to ensure high quality and efficient production use. The rapid programming algorithm reduces the time required to program the part and guar- antees reliable programming. Programming time is typically only 100s/byte. The integrated product identification code electronically identifies the device and manufacturer. This feature is used by industry standard programming equipment to select the proper pro- gramming algorithms and voltages. 0570HEPROM4/112. Pin configurations 32-lead PLCC 32-lead PDIP Pin name Function Top view Top view A0 - A17 Addresses VPP 1 32 VCC O0 - O7 Outputs A16 2 31 PGM CE Chip enable A15 3 30 A17 A7 5 29 A14 A12 4 29 A14 OE Output enable A6 6 28 A13 A7 5 28 A13 A5 7 27 A8 PGM Program strobe A6 6 27 A8 A4 8 26 A9 A5 7 26 A9 A3 9 25 A11 A4 8 25 A11 A2 10 24 OE A3 9 24 OE A1 11 23 A10 A2 10 23 A10 A0 12 22 CE A1 11 22 CE O0 13 21 07 A0 12 21 07 O0 13 20 06 O1 14 19 05 O2 15 18 04 GND 16 17 03 3. System considerations Switching between active and standby conditions via the chip enable pin may produce transient voltage excursions. Unless accommodated by the system design, these transients may exceed datasheet limits, resulting in device nonconformance. At a minimum, a 0.1F, high-frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the V and ground terminals of the device, as close to the device as possible. CC Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7F bulk electrolytic capacitor should be utilized, again connected between the V and ground terminals. This capacitor should be positioned as CC close as possible to the point where the power supply is connected to the array. Figure 3-1. Block diagram 2 Atmel AT27C020 0570HEPROM4/11 01 14 4 A12 02 15 3 A15 GND 16 2 A16 03 17 1 VPP 04 18 32 VCC 05 19 31 PGM 06 20 30 A17