CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS Rev 1C Data Sheet CDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS FEATURES General Description n 20/40/50/65/80MSPS max sampling rate The CDK8307 is a high performance low power octal analog-to-digital n Low Power Dissipation converter (ADC). The ADC employs internal reference circuitry, a serial control 23mW/channel at 20MSPS interface and serial LVDS output data, and is based on a proprietary structure. 35mW/channel at 40MSPS An integrated PLL multiplies the input sampling clock by a factor of 12 or 14, 41mW/channel at 50MSPS according to the LVDS output setting. The multiplied clock is used for data 51mW/channel at 65MSPS serialization and data output. Data and frame synchronization output clocks are 59mW/channel at 80MSPS supplied for data capture at the receiver. n 72.2dB SNR at 8MHz F IN n Various modes and configuration settings can be applied to the ADC through 0.5s startup time from Sleep the serial control interface (SPI). Each channel can be powered down inde- n 15s startup time from Power Down pendently and data format can be selected through this interface. A full chip n Internal reference circuitry requires no idle mode can be set by a single external pin. Register settings determines the external components exact function of this external pin. n Internal offset correction n The CDK8307 is designed to easily interface with field-programmable gate Reduced power dissipation modes available arrays (FPGAs) from several vendors. 34mW/channel at 50MSPS 71.5dB SNR at 8MHz F IN The very low startup times of the CDK8307 allow significant power reduction n Coarse and fine gain control in duty-cycled systems, by utilizing the Sleep Mode or Power Down Mode when n 1.8V supply voltage the receive path is idle. n Serial LVDS output 12- and 14-bit output available Block Diagram n Package alternatives TQFP-80 QFN-64 FCLKP APPLICATION S Serial Control Clock FCLKN PLL LVDS LCLKP Interface Input n Medical Imaging LCLKN n Wireless Infrastructure IP1 D1N Digital ADC LVDS n Test and Measurement Gain D1P IN1 n Instrumentation IP2 D2N Digital ADC LVDS Gain D2P IN2 IP8 D8N Digital ADC LVDS Gain D8P IN8 Exar Corporation www.exar.com 48720 Kato Road, Fremont CA 94538, USA Tel. +1 510 668-7000 - Fax. +1 510 668-7001 RESETN CSN SCLK SDATA CLKP CLKN PD AVDD AVSS DVDD DVSSCDK8307 12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS Rev 1C Data Sheet Table 6. LVDS Output Drive Strength for Table of Contents LCLK, FCLK, and Data ............................... 19 Features .................................................................. 1 Table 7. LVDS Internal Termination Applications ............................................................ 1 Programmability ....................................... 20 General Description ................................................ 1 Table 8. LVDS Output Internal Termination .............. 20 Block Diagram ........................................................ 1 Table 9. Analog Input Invert ................................... 20 Table of Contents ................................................... 2 Table 10. LVDS Test Patterns .................................. 21 Ordering Information ............................................. 3 Table 11. Programmable Gain ................................. 21 Pin Configurations .................................................. 4 Table 12. Gain Setting for Channels 1-8 .................. 22 Pin Assignments .................................................. 5-8 Table 13. LVDS Clock Programmability and Absolute Maximum Ratings ................................... 9 Data Output Modes ................................. 22 Reliability Information ........................................... 9 Figure 6. Phase Programmability Modes for LCLK ..... 23 ESD Protection ........................................................ 9 Figure 7. SDR Interface Modes ............................... 23 Recommended Operating Conditions .................... 9 Table 14. Number of Serial Output Bits ................... 23 Electrical Characteristics ...................................... 10 Figure 8. LVDS Output Timing Adjustment .............. 24 Electrical Characteristics CDK8307A ............10-11 Table 15. Full Scale Control .................................... 24 Electrical Characteristics CDK8307B ................ 11 Table 16. Register Values with Corresponding Electrical Characteristics CDK8307C ............11-12 Charge in Full-Scale Range ...................... 25 Electrical Characteristics CDK8307D ............12-13 Table 17. Clock Frequency ...................................... 25 Electrical Characteristics CDK8307E ................ 13 Table 18. Clock Frequency Settings ......................... 25 Digital and Timing Electrical Characteristics ..13-14 Table 19. Performance Control................................ 25 LVDS Timing Diagrams ......................................... 15 Table 20. Performance Control Settings ................... 26 Figure 1. 12-bit Output, DDR Mode ......................... 15 Table 21. External Common Mode Voltage Figure 2. 14-bit Output, DDR Mode ......................... 15 Buffer Driving Strength ........................... 26 Figure 3. 12-bit Output, SDR Mode ......................... 15 Theory of Operation ............................................. 27 Figure 4. Data Timing ............................................ 15 Recommended Usage ........................................... 27 Serial Interface ..................................................... 16 Analog Input ......................................................... 27 Timing Diagram .................................................... 16 Figure 9. Input Configuration Diagram ................ 27 Figure 5. Serial Port Interface Timing Diagram ..... 16 DC-Coupling .......................................................... 27 Table 1. Serial Port Interface Timing Definitions ... 16 Figure 10. DC-Coupled Input .............................. 27 Register Initialization ............................................. 16 AC-Coupling .......................................................... 28 Serial Register Map ..........................................17-18 Figure 11. Transformer Coupled Input ................. 28 Table 2. Summary of Functions Supported Figure 12. AC-Coupled Input .............................. 28 by Serial Interface ................................17-18 Figure 13. Alternative Input Network ................... 28 Clock Input and Jitter Considerations ...................... 29 Description of Serial Registers ........................18-25 Mechanical Dimensions ...................................30-31 Table 3. Software Reset ......................................... 18 QFN-64 Package.................................................... 30 Table 4. Power-Down Modes .................................. 18 TQFP-80 Package .................................................. 31 Table 5. LVDS Drive Strength Programmability ......... 19 2009-2013 Exar Corporation 2/31 Rev 1C