GS88218/36CB/D-xxxI
333 MHz150 MHz
512K x 18, 256K x 36
119- and 165-Bump BGA
2.5 V or 3.3 V V
DD
Industrial Temp
9Mb SCD/DCD Sync Burst SRAMs
2.5 V or 3.3 V I/O
Data Output Register. Holding FT high places the RAM in
Features
Pipeline mode, activating the rising-edge-triggered Data Output
FT pin for user-configurable flow through or pipeline operation
Register.
Single/Dual Cycle Deselect selectable
IEEE 1149.1 JTAG-compatible Boundary Scan
SCD and DCD Pipelined Reads
On-chip read parity checking; even or odd selectable
The GS88218/36C88218/36C is a SCD (Single Cycle
ZQ mode pin for user-selectable high/low output drive
Deselect) and DCD (Dual Cycle Deselect) pipelined
2.5 V or 3.3 V +10%/10% core power supply
synchronous SRAM. DCD SRAMs pipeline disable commands
2.5 V or 3.3 V I/O supply
to the same degree as read commands. SCD SRAMs pipeline
LBO pin for Linear or Interleaved Burst mode
deselect commands one stage less than read commands. SCD
Internal input resistors on mode pins allow floating mode pins
RAMs begin turning off their outputs immediately after the
Default to SCD x18/x36 Interleaved Pipeline mode
deselect command has been captured in the input registers.
Byte Write (BW) and/or Global Write (GW) operation
DCD RAMs hold the deselect command for one full cycle and
Internal self-timed write cycle
then begin turning off their outputs just after the second rising
Automatic power-down for portable applications
edge of clock. The user may configure this SRAM for either
JEDEC-standard 119- and 165-bump BGA packages
mode of operation using the SCD mode input.
RoHS-Compliant 119-bump and 165-bump BGA packages
Byte Write and Global Write
available
Byte write operation is performed by using Byte Write enable
Functional Description
(BW) input combined with one or more individual byte write
Applications
signals (Bx). In addition, Global Write (GW) is available for
The GS88218/36C is a 9,437,184-bit high performance
writing all bytes at one time, regardless of the Byte Write
synchronous SRAM with a 2-bit burst address counter. Although
control inputs.
of a type originally developed for Level 2 Cache applications
FLXDrive
supporting high performance CPUs, the device now finds
The ZQ pin allows selection between high drive strength (ZQ low)
application in synchronous SRAM applications, ranging from
for multi-drop bus applications and normal drive strength (ZQ
DSP main store to networking chip set support.
floating or high) point-to-point applications. See the Output Driver
Controls
Characteristics chart for details.
Addresses, data I/Os, chip enable (E1), address burst control
Sleep Mode
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
Low power (Sleep mode) is attained through the assertion
GW) are synchronous and are controlled by a positive-edge-
(High) of the ZZ signal, or by stopping the clock (CK).
triggered clock input (CK). Output enable (G) and power down
Memory data is retained during Sleep mode.
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
Core and Interface Voltages
with either ADSP or ADSC inputs. In Burst mode, subsequent
The GS88218/36C operates on a 2.5 V or 3.3 V power supply.
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in All input are 3.3 V and 2.5 V compatible. Separate output
either linear or interleave order with the Linear Burst Order (LBO) power (V ) pins are used to decouple output noise from the
DDQ
input. The Burst function need not be used. New addresses can be
internal circuits and are 3.3 V and 2.5 V compatible.
loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Parameter Synopsis
-333I -300I -250I -200I -150I Unit
t 2.5 2.5 2.5 3.0 3.8 ns
KQ
3.0 3.3 4.0 5.0 6.7 ns
tCycle
Pipeline
3-1-1-1
Curr (x18) 260 245 215 190 160 mA
Curr (x32/x36) 300 280 245 215 180 mA
t
4.5 5.0 5.5 6.5 7.5 ns
KQ
4.5 5.0 5.5 6.5 7.5 ns
Flow Through tCycle
2-1-1-1
Curr (x18) 200 185 180 160 148 mA
Curr (x32/x36) 225 210 200 180 165 mA
Rev: 1.05 7/2012 1/35 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see GS88218/36CB/D-xxxI
165 Bump BGAx18 Commom I/OTop View (Package D)
1 2 3 4 5 6 7 8 9 10 11
A NC A E1 BB NC E3 BW ADSC ADV A A A
B NC A E2 NC BA CK GW G ADSP A NC B
C NC NC V V V V V V V NC DQA C
DDQ SS SS SS SS SS DDQ
D NC DQB V V V V V V V NC DQA D
DDQ DD SS SS SS DD DDQ
E NC DQB V V V V V V V NC DQA E
DDQ DD SS SS SS DD DDQ
F NC DQB V V V V V V V NC DQA F
DDQ DD SS SS SS DD DDQ
G NC DQB V V V V V V V NC DQA G
DDQ DD SS SS SS DD DDQ
H FT MCL NC V V V V V NC ZQ ZZ H
DD SS SS SS DD
J DQB NC V V V V V V V DQA NC J
DDQ DD SS SS SS DD DDQ
K DQB NC V V V V V V V DQA NC K
DDQ DD SS SS SS DD DDQ
L DQB NC V V V V V V V DQA NC L
DDQ DD SS SS SS DD DDQ
M DQB NC V V V V V V V DQA NC M
DDQ DD SS SS SS DD DDQ
N DQB SCD V V NC NC NC V V NC NC N
DDQ SS SS DDQ
P NC NC A A TDI A1 TDO A A A A P
R LBO NC A A TMS A0 TCK A A A A R
11 x 15 Bump BGA13mm x 15 mm Body1.0 mm Bump Pitch
Rev: 1.05 7/2012 2/35 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see