EV12DS400AMZP
MilitaryGrade
Lowpower12bit4.5GSpsDigitaltoAnalog
Converterwith4/2:1Multiplexer
DatasheetDS1163
Inputdatacheckbitfortiminginterfacewith
MAINFEATURES
FPGAcheck(IDC)
12bitresolution
Timingviolationflags(setuporhold)forFPGA
4.5GSpsguaranteedconversionrate
communicationmonitoring(TVF)
3dBAnalogoutputBandwidthof7GHz
Diodefordiejunctiontemperaturemonitoring
4:1or2:1integratedparallelMUX(selectable)
LVDSdifferentialdatainputandDSPclockoutput.
Selectableoutputmodes:
Analogoutputdifferentialswing:1Vpp(100
ReturntoZero(RTZ),NonReturntoZero(NRZ),Narrow
differentialimpedance)
ReturnToZero(NRTZ)andRadioFrequency(RF)
Poweronreset
Lowlatencytime
Externalresetthatcanbeusedforsynchronizationof
2.6WattPowerDissipation(in4:1MUX)
multipleDACs
3WiresSerialInterface
Powersupplies:3.3V(Digital),3.3V&5V(Analog)
Functions:
FpBGApackage(15x15mmbodysize,1mmpitch)
SelectableMUXratio4:1(upto4.5GSps),2:1(upto
3.2GSps)
Userfriendlyfunctions,digitallycontrolledthrough
PERFORMANCES
a3WSIserialinterface:
Broadband:NPRat14dBFSLoadingFactor(90%of
GainAdjustment
fullNyquistzone),
Outputclockdivisionselection(possibilitytochange
st
1 Nyquist(NRTZ):NPR=47.5dB,9.4BitEquivalentat
thedivisionratiooftheDSPclock)(OCDS)
Fs=4.5GSps
ReshapedPulseWidth(RPW)andReshapedPulse
nd
2 Nyquist(NRTZ):NPR=42dB,8.5Bit
Begin(RPB)adjustmentsfor performance
EquivalentatFs=4.5GSps
optimization
rd
Clockphaseshiftselectforsynchronizationwith 3 Nyquist(RF):NPR=39dB,8BitEquivalentat
DSP(PSS[2:0])
Fs=4.5GSps
InputUnderClockingModeby1/2/4(IUCM)
DOCSIS3.0Compatible
DirectaccessavailableforbitOCDSandPSS
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e2vtechnologies(uk)limited,WaterhouseLane,Chelmsford,EssexCM12QUUnitedKingdomHoldingCompany:e2vtechnologiesplc
Telephone:+44(0)1245493493Facsimile:+44(0)1245492492
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1163BBDC03/16
e2vtechnologies(uk)limited2016EV12DS400AMZP
1. BLOCKDIAGRAM
Figure11. Simplifiedblockdiagram
MODE
Latches Latches
MUX
[1:0]
FPGA
24 A 24
24 B 24
DAC
4 data ports
Core
(12-bit 1st 24 2
(NRZ,
2nd
M/S
differential) OUT,
RTZ,
M/S
24 24
OUTN
C NRTZ,
RF)
24 24
D
Port Select DIODE
1
GA
TVF
FPGA
IDC_P
2
TIMING
IDC_N
2
DSP CLOCK CLOCK CLOCK
DSP
3WSI
PHASE SHIFT DIV/X BUFFER Reset_n
DSPN
2
3
PSS[2:0]
OCDS
sclk,
SYNC, CLK, CLKN
sdata,
SYNCN
sld_n
2. DESCRIPTION
TheEV12DS400Aisa12bit4.5GSpsDACwithanintegrated4:1or2:1multiplexerand7GHzoutput
bandwidth,allowingeasyinterfacewithstandardFPGAsthankstouserfriendlyfeaturessuchasDSP
clock,OCDS,PSS,TVF.
Itembeds4differentoutputmodes(NRZ,RTZ,NRTZandRF)thatallowperformanceoptimizations
dependingontheNyquistzoneofinterest.
2
1163BBDC03/16
e2vtechnologies(uk)limited2016